PDP-9 control memory

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Description of the PDP-9 control memory contents. The control memory is a read-only core memory which consists of 64 process words (i.e. microwords) of 36 bits each.

Program listing

PDP-9 control memory listing.

Meaning of control bits

Position Name Description
00 SUB Subtract gate
01 EAE
02 EAE-R
03 MBO Memory buffer output gate
04 MBI Memory buffer input gate
05 SKPI Skip input
06 ACO Accumulator output gate
07 ACI Accumulator input gate
08 IRI Instruction regster input gate
09 ARO Arithmetic register output gate
10 ARI Arithmetic register input gate
11 CJIT CAL/JMS/interrupt transfer gate
12 PCO Program counter output gate
13 PCI Program counter input gate
14 EAE-P
15 MQO Multiplier/quotient output gate
16 MQI Multiplier/quotient input gate
17 DEI Defer/execute initiate
18 LI Link input gate
19 AND AND instruction gate
20 TI Test for indirect addressing
21 DONE Instruction done gate
22 AXS ADD/XOR/SAD instruction gate
23-28 CMA 0-5 Address for next process word, possibly modified
29 EXT External transfer gate (program break)
30 CONT Continue to next process word
31 +1 Increment the ADR
32 SM Start memory cycle
33 ADSO Address switches output gate
34 KEY Key gate
35 DCH

CMA modification

The control memory address, CMA, from process word bits 23-28 is heavily modified by random logic before being used for addressing the control memory.

  • In address range 00-07 the CMA is OR'ed with a value that depends on the switches:
Value Switch
1 EXAMINE, DEPOSIT, or READ IN (first word)
2 READ IN (last word)
7 Maintenance panel test mode.
  • CMA 30 from word 24 is OR'ed with 1 or 2 depending on the result of the TI control bit.
  • Data channel requests will similarly "boost" the address.
  • In address range 60-77, the lower four bits come from the upper four bits of the instruction register. Hence each process word in this range implements one of the 16 instructions.

Wiring matrix

PDP-9 control memory wiring matrix.

Matrix decoded to binary and symbolic form

Address Process word bits Symbolic description
00 000000000000000000000000000000000000 CMA/00
01 000010000000000000000000101010001100 MBI ADSO SM CMA/25
02 000000000100000000000000110110001000 ARO SM CMA/33
03 000010000100000000000000101010011000 MBI ARO +1 SM CMA/25
04 000000000000000000000000000000000000 CMA/00
05 000010010010000010100000101110100010 MBI ACI ARI MQI LI KEY CONT CMA/27
06 000010000000010000000000100010001100 MBI PCI ADSO SM CMA/21
07 000010000100000000000000100100110000 MBI ARO +1 CONT CMA/22
10 000000000000100000000000100010001000 PCO SM CMA/21
11 000000001000000000000000110001001000 IRI EXT SM CMA/30
12 000000101010000000000000101000000000 ACO IRI ARI CMA/24
13 000000000010000000000000011100100000 ARI CONT CMA/16
14 000000000100000000000000111110001000 ARO SM CMA/37
15 000000000000000000000000000000000000 CMA/00
16 000000000000000000000000111100001000 SM CMA/36
17 000100000000000000000100010000000000 MBO DONE CMA/10
20 000000000000000000000100010000100000 DONE CONT CMA/10
21 000100000000010000000000010100110000 MBO PCI +1 CONT CMA/12
22 000100010010010010000000001110000100 MBO ACI ARI PCI MQI ADSO CMA/07
23 000100000001000000000001100000110000 MBO CJIT +1 CONT CMA/60
24 000000000000000000001000110000001000 TI SM CMA/30
25 000100000010000000000000101100000010 MBO ARI KEY CMA/26
26 000000000000100000000000100010001000 PCO SM CMA/21
27 000000000000000000000000000000000000 CMA/00
30 000000000001000001000001100000000000 CJIT DEI CMA/60
31 000000000000000001000000101000000000 DEI CMA/24
32 000000000010100000000000100110100000 ARI PCO CONT CMA/23
33 000000001000000000000000101000000000 IRI CMA/24
34 000100000010000000000000010000010001 MBO ARI +1 DCH CMA/10
35 000000000000000000000000000000000000 CMA/00
36 000000000000000000000000011110000001 DCH CMA/17
37 000000000000000000000000010110000001 DCH CMA/13
40 010000000000000000000100010000000000 EAE DONE CMA/10
41 010000100000000010000001011000100000 EAE ACO MQI CONT CMA/54
42 001000100000000010000001011010100000 EAE-R ACO MQI CONT CMA/55
43 010000010000000000000001000010100000 EAE ACI CONT CMA/41
44 000000000000000000000000000000000000 CMA/00
45 000000000000000000000000000000000000 CMA/00
46 000000000000000000000000000000000000 CMA/00
47 000000000000000000000000000000000000 CMA/00
50 000000000010001100000001000100100000 ARI EAE-P MQO CONT CMA/42
51 000010000000100000000001010100001000 MBI PCO SM CMA/52
52 000100000000010000100001010000010000 MBO PCI LI +1 CMA/50
53 001000000010000100000001011100100000 EAE-R ARI MQO CONT CMA/56
54 001000010000000000000001000000100000 EAE-R ACI CONT CMA/40
55 000000010100001000000001010110100000 ACI ARO EAE-P CONT CMA/53
56 000000100000001010000001011110100000 ACO EAE-P MQI CONT CMA/57
57 001000010100000000000001000000100000 EAE-R ACI ARO CONT CMA/40
60 000010000100000000000100010000100000 MBI ARO DONE CONT CMA/10
61 000010100000000000000100010000100000 MBI ACO DONE CONT CMA/10
62 000010000100000000000100010000100000 MBI ARO DONE CONT CMA/10
63 000010000000000000000100010000100000 MBI DONE CONT CMA/10
64 000100010000000000000100010000100000 MBO ACI DONE CONT CMA/10
65 100000010100000000000110010000100000 SUB ACI ARO DONE AXS CONT CMA/10
66 000100010100000000100110010000100000 MBO ACI ARO LI DONE AXS CONT CMA/10
67 000100010100000000100100010000100000 MBO ACI ARO LI DONE CONT CMA/10
70 000000000000000000001000110110001000 TI SM CMA/33
71 000101000010000000000100010000100000 MBO SKPI ARI DONE CONT CMA/10
72 000100010100000000010100010000100000 MBO ACI ARO AND DONE CONT CMA/10
73 100001100010000000000110010000100000 SUB SKPI ACO ARI DONE AXS CONT CMA/10
74 000100000000010000100100010000100000 MBO PCI LI DONE CONT CMA/10
75 010000100010000000100001000110100000 EAE ACO ARI LI CONT CMA/43
76 000000000000000000000000100000000000 CMA/20
77 000001010000000000100100010000100000 SKPI ACI LI DONE CONT CMA/10


The control memory region 00-07 is dedicated to implementing actions for the console panel switches. When the machine is powered on, control memory loops in a "nop" word at CMA 00. When the START switch is pressed, the CMA is "boosted" to 06 by random logic decoding the state of the switches.

  • 06: ADSO MBI PCI SM CMA/21
    ADSO gates output from the address switches; MBI and PCI gates input to the MB and PC registers. SM starts a new memory cycle. Processing enters the fetch phase at CMA 21.

The control memory region 10-33 is mostly dedicated to fetch, defer, and execute instruction cycles. The normal start of the instruction flow is at CMA 10. All instructions end by looping back there.

  • 10: PCO SM CMA/21
    PCO gates output from the PC register. Random logic sets MBI which gates input to the MB register, thus setting it to PC. SM starts memory access.
  • A new memory cycle starts, reading MB into MA.
  • 21: MBO +1 PCI CONT CMA/12
    MBO puts MB into the adder, and +1 increments the address by one. The sum is put into PC.
  • The read portion of the memory cycle is now ready. Random logic sets SAO and MBI, which transfers data from the memory SA "sense amplifiers" to MB.
  • 12: IRI ACO ARI CMA/24
    IRI sets the five-bit IR register from SA; four bits are for the opcode and the last bit is for address indirection. ACO and ARI copies the accumulator contents to the AR register.
  • 24: TI SM CMA/30
    TI makes a check for indirect addressing. SM starts a new memory access to retrieve the instruction operand.
  • A new memory cycle starts, reading MB into MA.
  • At this point, CMA 30 may be "boosted" by random logic. If there's indirect addressing, processing continues at CMA 31. If the IR holds a CAL, DAC, JMS, or DZM instruction, processing continues at 32. For XCT, JMP, EAE, IOT, or OPR without indirect addressing, the CMA is short-circuited directly to 7x and dispatching to the 60-77 region. Otherwise, proceed to the unboosted address 30.
    • 30: DEI CJIT CMA/60
      DEI ensures MBI and SAO are set to retrieve the memory operand. CJIT activates a check for ISZ with operand 0, and increments the PC if so. The next CMA is "boosted" by putting the instruction opcode in the lower four bits, thus dispatching to CMA 60-77.
    • 31: DEI CMA/24
      DEI clears the indirect addressing bit in IR4. The memory cycle read phase has put the indirect address in MB. Processing loops back to CMA 24 to start a new memory cycle using MB as the address. There can't be any more loop since IR4 was cleared.
    • 32: ARI PCO CONT CMA/23
      The PC is saved in the AR register for the benefit of CAL and JMS; later it will be written to memory location MA.
      23: MBO +1 CJIT CONT CMA/60
      MBO sends the MB through the adder, and +1 increments it. CJIT checks for CAL or JMS to set PCI and store the incremented result to the PC. Dispatch to CMA 60-77.
  • The instruction execute phase dispatches to the CMA region 60-77. The memory cycle read phase has put the operand in MB, and the write phase is ready to receive the result. Three instructions, XCT, EAE, and IOT, have a more complicated flow.
    • 60-77: [various] DONE CONT CMA/10
      Most instructions do their thing and loop back to CMA 10.
    • XCT 70: TI SM CMA/33
      Start a new memory access to fetch the instruction.
      33: IRI CMA/24
      Put the opcode in IR and loop back to CMA 24.
      Extended arithmetic is implemented in CMA 40-57 and will eventually reach a process word with DONE CONT CMA/10.
    • IOT 76: CMA/20
      Random logic does all the work for the I/O transfer instructions.
      20: DONE CONT CMA/10
      Finish I/O and loop back to CMA 10.

The control memory region 11-37 is shared with instruction flow, but also implements data break, interrupt, and console panel deposit, examine, and read-in functions.

Region 40-57 is dedicated to the EAE instructions.

Each process word in the region 60-77 implements the execution phase of one of the 16 PDP-9 instructions.