Reduced Instruction Set Computer

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A Reduced Instruction Set Computer (usually abbreviated to RISC) is one from a school of CPU architecture in which the goal is to produce a design whose object code is optimized toward producing the fastest possible instruction execution time, as part of a overall system architecture which maximizes the performance at minimum cost.

The original RISC machine, the IBM 801, was designed together with its compiler, the concept being that functionality would be divided between the two in such a way as to achieve the cost/performance goals, with the compiler doing things to make the hardware as simple (and thus fast) as possible. While the compiler would be more complex, as it had to include extra mechanism to do things that the hardware did not do, the engineering costs of that would be amortized over all the units, whereas extra hardware is a cost in every unit.

To achieve this goal, the instructions are made as simple as possible; the machines are generally load-store architectures, and most instructions only perform a single reference to main memory (other than their own fetch).

One engineering technique used internally is to look for the longest signal path through the CPU, and try and get rid of the instruction/feature which uses it - this will allow the machine's cycle time to be reduced, i.e. increasing its clock speed.

Another way of looking at RISC is that it does not try and maximize the instruction density - i.e. the number of memory bits needed to hold a given set of programming functionality. This means that it did not maximize the efficiency of the main memory's bandwidth (and space, although the latter is no longer as important a goal as it used to be, with the advent of extemely large main memories typical on modern machines), that having been the principle bottleneck in older computers (particularly those using core memory).

See also