View source for M-bus

The '''M-bus''' from [[Digital Equipment Corporation|DEC]] was a unique [[synchronous]] [[bus]] used in some [[VAXstation]]s. It supported a 32-bit [[main memory]] [[address space]], and 32-bit data transfers (although memory operations always transferred 4 longwords of data at a time).

[[Arbitration]] for use of the M-bus used a distributed [[Least Recently Used algorithm|LRU]] mechanism. The M-bus had considerable support for [[cache]]s, including the capability to allow caches in [[Central Processing Unit|CPUs]] connected to the M-bus to maintain consistent data. The M-bus also supported [[interrupt]]s from [[peripheral]]s to CPUs. It used [[parity]] for [[error detection]].

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==External links==

* [http://www.bitsavers.org/pdf/dec/vax/35x0/firefox_MBusSpec_198712.pdf Firefox Workstation M-Bus Specification]

[[Category: DEC Buses]]