Difference between revisions of "Modified UNIBUS Device"
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'''Modified UNIBUS Device''' or '''MUD''' was [[DEC]]'s name for an I/O board slot in the [[backplane]]s of [[UNIBUS]] [[PDP-11]]s. It was a [[DEC card form factor|hex]] slot, and could hold any kind of device. | '''Modified UNIBUS Device''' or '''MUD''' was [[DEC]]'s name for an I/O board slot in the [[backplane]]s of [[UNIBUS]] [[PDP-11]]s. It was a [[DEC card form factor|hex]] slot, and could hold any kind of device. | ||
| − | It differed from the older [[Small Peripheral Controller]] slot in that it was a hex-height slot, and used the | + | It differed from the older [[Small Peripheral Controller]] slot in that it was a hex-height slot, and used the pins (in the A/B rows) to carry UNIBUS signals (pin-compatible with the usual dual UNIBUS slot); a number of lines for communication between a parity controller, and parity-capable memory boards plugged into that backplane; and additional voltages (primarily for core memory). |
| + | |||
| + | ==Grants== | ||
MUD slots, like SPC slots, were wired to bring all 5 UNIBUS grant lines through the device; this was performed in rows C (for NPG) and D (for BGx), not the 'pseudo-UNIBUS' rows A/B, since the standard UNIBUS dual connector only contains one pin per grant (suitable only for an 'in' or 'out' UNIBUS connector), not separate 'grant in' and 'grant out' pins (as on the [[QBUS]]). | MUD slots, like SPC slots, were wired to bring all 5 UNIBUS grant lines through the device; this was performed in rows C (for NPG) and D (for BGx), not the 'pseudo-UNIBUS' rows A/B, since the standard UNIBUS dual connector only contains one pin per grant (suitable only for an 'in' or 'out' UNIBUS connector), not separate 'grant in' and 'grant out' pins (as on the [[QBUS]]). | ||
A board plugged into a MUD slot generally had a header which routed the grant (and matching request) line for the desired priority level to the on-board interrupt circuity, and passed the other grant lines through. The DMA (NPG) grant line generally had a jumper on the backplane, which had to be removed if a DMA device was plugged into the slot. Un-occupied slots needed to have a grant continuity card installed. | A board plugged into a MUD slot generally had a header which routed the grant (and matching request) line for the desired priority level to the on-board interrupt circuity, and passed the other grant lines through. The DMA (NPG) grant line generally had a jumper on the backplane, which had to be removed if a DMA device was plugged into the slot. Un-occupied slots needed to have a grant continuity card installed. | ||
| + | |||
| + | ==Added signals== | ||
| + | |||
| + | The added lines for communication between a parity controller and parity-capable memory boards were Parity Detect (used to let memory boards know that a parity controller is present); Internal SSYN (used by memory boards to let the parity controller know that their data is ready); and Parity P0 and Parity P1 (parity data). | ||
| + | |||
| + | The additional voltages were + and -15V, -5V, and +20V. | ||
| + | |||
| + | ==Pinout== | ||
| + | |||
| + | The pins which changed from standard UNIBUS to MUD are: | ||
| + | |||
| + | * AB2 - Test Point | ||
| + | * AN1 - Parity P1 | ||
| + | * AP1 - Parity P0 | ||
| + | * AR1 - -15/12 Battery | ||
| + | * AS1 - -15/12 Battery | ||
| + | * AU1 - +20V (core) | ||
| + | * AV1 - +20V (core) | ||
| + | * AV2 - +20V (core) | ||
| + | * BA1 - Reserved | ||
| + | * BB1 - Reserved | ||
| + | * BB2 - Test Point | ||
| + | * BD1 - +5V Battery | ||
| + | * BE1 - Internal SSYN | ||
| + | * BE2 - Parity Detect | ||
| + | * BV2 - -5V (core) | ||
Revision as of 14:37, 22 July 2016
Modified UNIBUS Device or MUD was DEC's name for an I/O board slot in the backplanes of UNIBUS PDP-11s. It was a hex slot, and could hold any kind of device.
It differed from the older Small Peripheral Controller slot in that it was a hex-height slot, and used the pins (in the A/B rows) to carry UNIBUS signals (pin-compatible with the usual dual UNIBUS slot); a number of lines for communication between a parity controller, and parity-capable memory boards plugged into that backplane; and additional voltages (primarily for core memory).
Grants
MUD slots, like SPC slots, were wired to bring all 5 UNIBUS grant lines through the device; this was performed in rows C (for NPG) and D (for BGx), not the 'pseudo-UNIBUS' rows A/B, since the standard UNIBUS dual connector only contains one pin per grant (suitable only for an 'in' or 'out' UNIBUS connector), not separate 'grant in' and 'grant out' pins (as on the QBUS).
A board plugged into a MUD slot generally had a header which routed the grant (and matching request) line for the desired priority level to the on-board interrupt circuity, and passed the other grant lines through. The DMA (NPG) grant line generally had a jumper on the backplane, which had to be removed if a DMA device was plugged into the slot. Un-occupied slots needed to have a grant continuity card installed.
Added signals
The added lines for communication between a parity controller and parity-capable memory boards were Parity Detect (used to let memory boards know that a parity controller is present); Internal SSYN (used by memory boards to let the parity controller know that their data is ready); and Parity P0 and Parity P1 (parity data).
The additional voltages were + and -15V, -5V, and +20V.
Pinout
The pins which changed from standard UNIBUS to MUD are:
- AB2 - Test Point
- AN1 - Parity P1
- AP1 - Parity P0
- AR1 - -15/12 Battery
- AS1 - -15/12 Battery
- AU1 - +20V (core)
- AV1 - +20V (core)
- AV2 - +20V (core)
- BA1 - Reserved
- BB1 - Reserved
- BB2 - Test Point
- BD1 - +5V Battery
- BE1 - Internal SSYN
- BE2 - Parity Detect
- BV2 - -5V (core)
