Difference between revisions of "KI10"
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| + | {{Infobox Machine | ||
| + | | name = KI10 | ||
| + | | manufacturer = [[Digital Equipment Corporation]] | ||
| + | | architecture = [[PDP-10]] | ||
| + | | year design started = December, 1969 | ||
| + | | year first shipped = May, 1972 | ||
| + | | form factor = [[mainframe]] | ||
| + | | word size = 36 bits | ||
| + | | physical address = 22 bits | ||
| + | | virtual address = 18 bits | ||
| + | | logic type = [[TTL]] [[IC]]s | ||
| + | | design type = clocked synchronous | ||
| + | | clock speed = 1 μsec | ||
| + | | memory speed = 1.0 μsec (fast), 1.8 μsec (slow) | ||
| + | | memory mgmt = [[paging]], 512-word pages | ||
| + | | operating system = [[TOPS-10]], [[TENEX]] | ||
| + | | predecessor = [[KA10]] | ||
| + | | successor = [[KL10]] | ||
| + | | price = US$200K (CPU), US$500K-1M (system) | ||
| + | }} | ||
| + | |||
The '''KI10''' was the second generation of [[PDP-10]] processors (themselves, exact re-implementations of the earlier [[PDP-6]] architecture). It was built out of [[TTL]] [[chip]]s, on [[FLIP CHIP]] cards. | The '''KI10''' was the second generation of [[PDP-10]] processors (themselves, exact re-implementations of the earlier [[PDP-6]] architecture). It was built out of [[TTL]] [[chip]]s, on [[FLIP CHIP]] cards. | ||
It was used in later[[DECsystem-10]] models, running [[TOPS-10]]. It was the first PDP-10 model to provide [[paging]] in its as-shipped form. | It was used in later[[DECsystem-10]] models, running [[TOPS-10]]. It was the first PDP-10 model to provide [[paging]] in its as-shipped form. | ||
Revision as of 23:28, 5 August 2017
| KI10 | |
| Manufacturer: | Digital Equipment Corporation |
|---|---|
| Architecture: | PDP-10 |
| Year Design Started: | December, 1969 |
| Year First Shipped: | May, 1972 |
| Form Factor: | mainframe |
| Word Size: | 36 bits |
| Logic Type: | TTL ICs |
| Design Type: | clocked synchronous |
| Clock Speed: | 1 μsec |
| Memory Speed: | 1.0 μsec (fast), 1.8 μsec (slow) |
| Physical Address Size: | 22 bits |
| Virtual Address Size: | 18 bits |
| Memory Management: | paging, 512-word pages |
| Operating System: | TOPS-10, TENEX |
| Predecessor(s): | KA10 |
| Successor(s): | KL10 |
| Price: | US$200K (CPU), US$500K-1M (system) |
The KI10 was the second generation of PDP-10 processors (themselves, exact re-implementations of the earlier PDP-6 architecture). It was built out of TTL chips, on FLIP CHIP cards.
It was used in laterDECsystem-10 models, running TOPS-10. It was the first PDP-10 model to provide paging in its as-shipped form.
