Difference between revisions of "KI10"
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| − | | logic type = [[TTL]] [[IC]]s | + | | logic type = [[transistor-transistor logic|TTL]] [[IC]]s |
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| − | The '''KI10''' was the second generation of [[PDP-10]] processors (themselves, exact re-implementations of the earlier [[PDP-6]] architecture). It was built out of [[TTL]] [[chip]]s, on [[FLIP CHIP]] cards. | + | The '''KI10''' was the second generation of [[PDP-10]] processors (themselves, exact re-implementations of the earlier [[PDP-6]] architecture). It was built out of [[transistor-transistor logic|TTL]] [[integrated circuit|chip]]s, on [[FLIP CHIP]] cards. |
It was used in later[[DECsystem-10]] models, running [[TOPS-10]]. Via a series of kludges, it was also possible to run [[TENEX]] on the as-shipped hardware. | It was used in later[[DECsystem-10]] models, running [[TOPS-10]]. Via a series of kludges, it was also possible to run [[TENEX]] on the as-shipped hardware. | ||
| − | It was the first PDP-10 model to provide [[paging]] in its as-shipped form. It was initially released in a single-[[ | + | It was the first PDP-10 model to provide [[paging]] in its as-shipped form. It was initially released in a single-[[central processing unit|CPU]] version; a two-CPU version was released later. |
[[Image:Sys37a.jpg|thumb|left|KI10 at Tymshare]] | [[Image:Sys37a.jpg|thumb|left|KI10 at Tymshare]] | ||
[[Category: PDP-10 Processors]] | [[Category: PDP-10 Processors]] | ||
Revision as of 08:40, 15 March 2018
| KI10 | |
| Manufacturer: | Digital Equipment Corporation |
|---|---|
| Architecture: | PDP-10 |
| Year Design Started: | December, 1969 |
| Year First Shipped: | May, 1972 |
| Form Factor: | mainframe |
| Word Size: | 36 bits |
| Logic Type: | TTL ICs |
| Design Type: | clocked synchronous |
| Clock Speed: | 1 μsec |
| Memory Speed: | 1.0 μsec (fast), 1.8 μsec (slow) |
| Physical Address Size: | 22 bits |
| Virtual Address Size: | 18 bits |
| Memory Management: | paging, 512-word pages |
| Operating System: | TOPS-10, TENEX, TYMCOM-X |
| Predecessor(s): | KA10 |
| Successor(s): | KL10 |
| Price: | US$200K (CPU), US$500K-1M (system) |
The KI10 was the second generation of PDP-10 processors (themselves, exact re-implementations of the earlier PDP-6 architecture). It was built out of TTL chips, on FLIP CHIP cards.
It was used in laterDECsystem-10 models, running TOPS-10. Via a series of kludges, it was also possible to run TENEX on the as-shipped hardware.
It was the first PDP-10 model to provide paging in its as-shipped form. It was initially released in a single-CPU version; a two-CPU version was released later.
