Difference between revisions of "Talk:UNIBUS parity"
From Computer History Wiki
(OK, done - and KL10 question) |
m (fmt typo) |
||
| Line 7: | Line 7: | ||
: OK, done - see what you think. | : OK, done - see what you think. | ||
| − | : Also, I wonder about the RH11 in the [[KL10]] front end - could | + | : Also, I wonder about the RH11 in the [[KL10]] front end - could it do 18-bit transfers over the front end's UNIBUS? ISTR that the RP's on that were double ported, and the [[RH10]] could get too them too, so maybe no need for the 18-bit mode on the front end (and probably not high enough performance anyway). [[User:Jnc|Jnc]] ([[User talk:Jnc|talk]]) 21:43, 23 January 2019 (CET) |
| − | it do 18-bit transfers over the front end's UNIBUS? ISTR that the RP's on that were double ported, and the [[RH10]] could get too them | ||
| − | too, so maybe no need for the 18-bit mode on the front end (and probably not high enough performance anyway). [[User:Jnc|Jnc]] ([[User talk:Jnc|talk]]) 21:43, 23 January 2019 (CET) | ||
Revision as of 21:44, 23 January 2019
18-bit mode
Would it be appropriate to mention 18-bit data on the UNIBUS here? I understand the KS10 and some of its devices could use the two parity bits for data. Maybe some of the 18-bit PDPs too? Larsbrinkhoff (talk) 12:40, 23 January 2019 (CET)
- Yeah, good idea. This hack is mentioned in a number of places (e.g. MX15-B Memory Multiplexer, RH11 MASSBUS controller, etc). Once I update here, I'll link them in.
- I wonder if this possibility was thought of up front, or if this hack was only developed later, when someone had a brainwave? Jnc (talk) 14:28, 23 January 2019 (CET)
- OK, done - see what you think.
- Also, I wonder about the RH11 in the KL10 front end - could it do 18-bit transfers over the front end's UNIBUS? ISTR that the RP's on that were double ported, and the RH10 could get too them too, so maybe no need for the 18-bit mode on the front end (and probably not high enough performance anyway). Jnc (talk) 21:43, 23 January 2019 (CET)
