RH11 MASSBUS controller
There are three models:
- The RH11-AB model, the most common version.
- The RH11-B model; it uses the M9725-YA card, which has an ECO which involves the two added one-shots in the lower left corner of drawing BCTB; the effect is not known.
- The RH11-C model; it uses the M9724-YA card, which has an ECO modifying the operation of 'Bus Hog' mode (see below).
The registers in the RH11 are only accesssible from the 'first' UNIBUS (UNIBUS 'A'); likewise, interrupts of the CPU are only possible via UNIBUS 'A'. (The interrupt grant lines on UNIBUS 'B" are only present on the backplane, they are not routed to any of the cards.) The RH11 can be set under software control to do DMA data transfers on either the first or second UNIBUS (UNIBUS 'B').
The 'A' UNIBUS has a mode where it can do two DMA cycles per grant. The 'B' UNIBUS can operate in so-called 'Bus Hog' mode (enabled by a jumper); in this mode, the RH11 can do block transfers without going through any UNIBUS arbitration cycles. (See Section 4.12.10, "BUS HOG Mode", pg. 4-22 [59 of the PDF] in the "RH11-AB Option Description" for details.) The RH11-C ECO breaks such blocks up into 16-word groups.
The RH11 has the capability to operate in 18-bit mode; in this mode, the PA and PB UNIBUS parity lines are used for data bits 16 and 17. The PDP-15 and KS10 made use of this capability, the latter with the RH11-C model.
Note that 18-bit mode is only available on the 'B' UNIBUS (which must be selected) if a jumper is removed; see Section 4.16 "Logic Diagram DBCE", pg. 4-28 (65 of the PDF) in the "RH11-AB Option Description" for details.
The RH11 contains 4 registers, plus a share of a fifth; they are
- RHCS1 - Control and Status 1 (shared)
- RHWC - Word Count
- RHBA - Bus Address
- RHCS2 - Control and Status 2
- RHDB - Data Buffer (for maintenance)
As is standard for the MASSBUS, all the other device registers are in the device.
Two of them hex-sized:
- M7294 - DBC - Data Buffer and Control
- M7295 - BCT - Bus Control
Two dual-sized cards containing controller logic:
- M7296 - CSR - Control and Status
- M7297 - PAC - Parity Generation and Checking
Three dual-height M5904 MASSBUS transceiver modules.
Optionally one or two single-height cards:
- M688 - UNIBUS Power Fail Driver
|1||UNIBUS A In||M7297 Parity||M7296 Control/Status|
|2||M7295 Bus Control|
|3||M7294 Data/Buffer Control|
|4||Unused||M5904 Transceiver||M688 - UNIBUS B Power Fail||Unused|
|5||Unused||M5904 Transceiver||M688 - UNIBUS A Power Fail||Unused|
|7||UNIBUS B Out||SPC|
|8||UNIBUS B In||SPC|
|9||UNIBUS A Out||SPC|
The order of the UNIBUS 'B' in/out and 'A' out slots is apparently to allow the use of an M9200 UNIBUS jumper to tie the two UNIBI together. (E.g. in the 'disk' RH11 in the KS10, where the CPU needs access to the device registers, interrupts, etc, which are on UNIBUS 'A', but also has to be connected to UNIBUS 'B', for 18-bit data transfers.)