Difference between revisions of "KE11-F Floating Instruction Set"
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The '''KE11-F Floating Instruction Set''' is the optional [[floating point]] unit for the [[KD11-A CPU]] of the [[PDP-11/40]]. It implements the [[PDP-11]] [[FIS floating point]], not the full [[FP11 floating point]]. | The '''KE11-F Floating Instruction Set''' is the optional [[floating point]] unit for the [[KD11-A CPU]] of the [[PDP-11/40]]. It implements the [[PDP-11]] [[FIS floating point]], not the full [[FP11 floating point]]. | ||
Revision as of 02:35, 19 September 2019
The KE11-F Floating Instruction Set is the optional floating point unit for the KD11-A CPU of the PDP-11/40. It implements the PDP-11 FIS floating point, not the full FP11 floating point.
Physically, it consists of a single quad board, the M7239, which plugs into a pre-wired slot in the CPU backplane.
It requires the installation of the KE11-E Extended Instruction Set, which allows the microcode of the basic CPU to be extended.
The KE11-F includes its own microcode ROM, which provides an additional 8 bits width of microcode (to control the data paths and registers on the M7239), but it also uses microcode stored on the KE11-E, to control registers and datapaths elsewhere.
Further reading
- "KE11-E and KE11-F Instruction Set Options Manual", EK-KE11E-TM-002
