Difference between revisions of "DRV11-WA General Purpose DMA Interface"
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[[Image:DRV11-WA.jpg|thumb|200px|right|DRV11-WA board]] | [[Image:DRV11-WA.jpg|thumb|200px|right|DRV11-WA board]] | ||
| − | The '''DRV11-WA Direct Memory Access Interface''' is a parallel | + | The '''DRV11-WA Direct Memory Access Interface''' is a [[parallel interface]] [[device controller]] for the [[QBUS]] which provided a pair of 16-[[bit]] parallel ports, one input, and one output. It uses [[Direct Memory Access|DMA]] to transfer data; it is a [[QBUS#Variable address size|Q22]] device. |
It is effectively a [[half-duplex]] device; it has only a single pair of [[bus]] [[address]] and word count [[register]]s. Directional control is by the [[user]]'s device specifying whether each cycle is a DATI, DATO, or DATIO. | It is effectively a [[half-duplex]] device; it has only a single pair of [[bus]] [[address]] and word count [[register]]s. Directional control is by the [[user]]'s device specifying whether each cycle is a DATI, DATO, or DATIO. | ||
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{{16bit-bitout}} | {{16bit-bitout}} | ||
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| − | [[Category:QBUS | + | [[Category: QBUS Parallel Interfaces]] |
Revision as of 03:01, 10 June 2020
The DRV11-WA Direct Memory Access Interface is a parallel interface device controller for the QBUS which provided a pair of 16-bit parallel ports, one input, and one output. It uses DMA to transfer data; it is a Q22 device.
It is effectively a half-duplex device; it has only a single pair of bus address and word count registers. Directional control is by the user's device specifying whether each cycle is a DATI, DATO, or DATIO.
It was a dual format card (M7651); connection to the user's device is via a pair of 40-pin Berg connectors.
Registers
The device has six control and buffer registers, which can be configured to any group of four sequential word locations in the I/O page (two pairs of registers share an address); the first DRV11-WA is normally configured to addresses 772410-72416.
| Register | Abbreviation | Address |
|---|---|---|
| Word Count Register | DRWCR | 767770 |
| Bus Address Register | DRBAR | 767772 |
| Bus Address Extension Register | DRBAE | 767772 |
| Control and Status Register | DRCSR | 767774 |
| Input Data Buffer Register | DRINBUF | 767776 (read) |
| Output Data Buffer Register | DROUTBUF | 767776 (write) |
To gain access to the BAE, reference the BAR; this sets an internal flag which sends the next reference to the BAR's address to the BAE. Referring to any register (e.g. reading the WCR) clears the flag. The two buffer registers share an address, responding to read or write cycles as the case might be.
