Difference between revisions of "DA11-F UNIBUS Window"
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| − | The '''DA11-F UNIBUS Window''' allows two [[UNIBUS]]es to be directly connected, to allow bus read/write cycles from a master on one to be answered by a slave on the other; this functionality is bi-directional. Although the DA11-F can ''generate'' [[interrupt]]s on either UNIBUS (in response to user commands given directly to it via its Control and Status Register), it cannot ''transfer'' interrupts (i.e. from one UNIBUS to the other). | + | The '''DA11-F UNIBUS Window''' allows two [[UNIBUS]]es to be directly connected, to allow bus read/write cycles (including [[Direct Memory Access|DMA]] cycles) from a master on one to be answered by a slave on the other; this functionality is bi-directional. Although the DA11-F can ''generate'' [[interrupt]]s on either UNIBUS (in response to user commands given directly to it via its Control and Status Register), it cannot ''transfer'' interrupts (i.e. from one UNIBUS to the other). |
| − | The DA11-F responds as a slave to bus cycles on each UNIBUS which are to be passed through; it then uses an [[Non-Processor Request and Grant|NPR]] | + | The DA11-F responds as a slave to bus cycles on each UNIBUS which are to be passed through; it then uses an [[Non-Processor Request and Grant|NPR]] DMA operation on the other UNIBUS to complete the cycle on the other, as a master. For write operations, the data is [[buffer]]ed in the DA11-F; therefore, simultaneous write operations on both buses can be handled. |
If a read cycle is requested on one UNIBUS, and a write simultaneously on the other, the read cycle takes precedence, and is completed before the write cycle can be completed. If read cycles are requested on both buses simultaneously, neither side can gain the needed control of the other; both requests are aborted, and both cycles will time-out. | If a read cycle is requested on one UNIBUS, and a write simultaneously on the other, the read cycle takes precedence, and is completed before the write cycle can be completed. If read cycles are requested on both buses simultaneously, neither side can gain the needed control of the other; both requests are aborted, and both cycles will time-out. | ||
Latest revision as of 23:01, 13 January 2022
The DA11-F UNIBUS Window allows two UNIBUSes to be directly connected, to allow bus read/write cycles (including DMA cycles) from a master on one to be answered by a slave on the other; this functionality is bi-directional. Although the DA11-F can generate interrupts on either UNIBUS (in response to user commands given directly to it via its Control and Status Register), it cannot transfer interrupts (i.e. from one UNIBUS to the other).
The DA11-F responds as a slave to bus cycles on each UNIBUS which are to be passed through; it then uses an NPR DMA operation on the other UNIBUS to complete the cycle on the other, as a master. For write operations, the data is buffered in the DA11-F; therefore, simultaneous write operations on both buses can be handled.
If a read cycle is requested on one UNIBUS, and a write simultaneously on the other, the read cycle takes precedence, and is completed before the write cycle can be completed. If read cycles are requested on both buses simultaneously, neither side can gain the needed control of the other; both requests are aborted, and both cycles will time-out.
The base address, and size, of the incoming window, on each UNIBUS, is set by configuration jumpers. The base address of the outgoing window is set by a register in the BA11-F.
Registers
Registers given in italic font are read-only; those in normal font are read-write.
| Register | Address |
|---|---|
| Control and Status Register | XXXX00 |
| Output Data Buffer Register | XXXX02 |
| Input Data Buffer Register | XXXX04 |
| Displacement Address Register | XXXX06 |
| Relocation Address Register | XXXX10 |
| Starting Address Register | XXXX12 |
| Vector Address Register | XXXX14 |
The first DA11-F in a system is usually assigned register addresses starting with 0764000 for the 'A' UNIBUS, and 0764020 for the 'B' UNIBUS; the second is usually assigned addresses starting with 0764020 for the 'A' UNIBUS, etc.
Implementation
It consists of a 4-slot custom system unit backplane, holding two pairs of two quad cards:
- M7284 Bus Control
- M7283 Bus to Bus Paths
Board locations are:
| Connector | ||||||
|---|---|---|---|---|---|---|
| Slot | A | B | C | D | E | F |
| 1 | UNIBUS A In | M7284 A Bus Control | ||||
| 2 | UNIBUS B Out | M7283 Bus to Bus Paths (odd bits) | ||||
| 3 | UNIBUS B In | M7283 Bus to Bus Paths (even bits) | ||||
| 4 | UNIBUS A Out | M7284 B Bus Control | ||||
Further reading
- DAll-F Unibus Window Engineering Drawings
External links
- DA-11F unibus window maintenance manual (DEC-11-HDAFA-A-D)
