Difference between revisions of "DR11-B parallel interface"

From Computer History Wiki
Jump to: navigation, search
m (typo, minor copyedits)
m (→‎External links: +manual)
 
(10 intermediate revisions by the same user not shown)
Line 1: Line 1:
−
The '''DR11-B''' was a parallel interface for the UNIBUS, one which used [[DMA]] to transfer data.  
+
The '''DR11-B''' was a [[parallel interface]] for the [[UNIBUS]], one which used [[Direct Memory Access|DMA]] to transfer data to a user device.
 +
 
 +
The interface between the DR11-B and the user device uses a number of unidirectional control lines (below), which control data transfer; and sets of three 'status' and 'control' lines, which appear in the Status and Command Register. By appropriate manipulation of the control lines, the user device can do byte or word cycles on the bus, perform read-modify-write bus cycles, or do block 'burst' bus transfers.
 +
 
 +
Data going to the user device is [[buffer]]ed in a set of [[latch]]es; data coming from the user device is ''not'' buffered, and must be held valid for the duration of the resultant bus cycle.
 +
 
 +
==Registers==
 +
 
 +
{| border=1
 +
! Register !! Abbreviation !! Address
 +
|-
 +
|Word Count Register            || DRWC || 772410
 +
|-
 +
|Bus Address Register          || DRBA || 772412
 +
|-
 +
|Status and Command Register    || DRST || 772414
 +
|-
 +
|Data Buffer Register          || DRDB || 772416
 +
|}
 +
 
 +
The [[address]]es shown are for the first DR11-B in a system; additional ones are normally set to be at 772430, 772450, 772470, etc.
 +
 
 +
===772410: Word Count Register (DRWC)===
 +
{{16bit-header}}
 +
| colspan=16 | WC15 <---> WC00
 +
{{16bit-bitout}}
 +
 
 +
===772412: Bus Address Register (DRBA)===
 +
{{16bit-header}}
 +
| colspan=16 | BA15 <---> BA00
 +
{{16bit-bitout}}
 +
 
 +
===772414: Status and Command Register (DRST)===
 +
{{16bit-header}}
 +
| ERROR || NEX || ATTN || MAINT || colspan=3 | DSTAT A-C || CYCLE || READY || IE || colspan=2 | XBA16-17 || colspan=3 | FNCT1-3 || GO
 +
{{16bit-bitout}}
 +
 
 +
===772416: Data Buffer Register (DRDB)===
 +
{{16bit-header}}
 +
| colspan=16 | Data15 <---> Data00
 +
{{16bit-bitout}}
 +
 
 +
Note: Unlike most DEC DMA devices, an overflow in the Bus Address Register does not carry into the Extended Memory bits in the CSR.
 +
 
 +
==User Device Interface==
 +
 
 +
===User Input Signals===
 +
 
 +
{| class="wikitable"
 +
! Signal Name !! Count !! Function
 +
|-
 +
| DAT IN || 16 || Data from user device
 +
|-
 +
| CONTROL || 2 || Specify type of UNIBUS cycle (DATI, etc)
 +
|-
 +
| CYCLE REQ || 2 || Either one can set the CYCLE bit, which causes a bus cycle
 +
|-
 +
| WC INC ENB || 1 || Word Count Increment Enable
 +
|-
 +
| BA INC ENB || 1 || Bus Address Increment Enable
 +
|-
 +
| A00 || 1 || Bus Address Bit 0
 +
|-
 +
| DSTAT || 3 || Device Status Bits
 +
|-
 +
| ATTN || 1 || Attention bit in the DRST
 +
|-
 +
| SINGLE CYCLE || 1 || Controls use of burst mode for bus cycles
 +
|}
 +
 
 +
===User Output Signals===
 +
 
 +
{| class="wikitable"
 +
! Signal Name !! Count !! Function
 +
|-
 +
| DAT OUT || 16 || Data to user device
 +
|-
 +
| INITIALIZE || 1 || UNIBUS INIT or interlock error
 +
|-
 +
| FNCT || 3 || Function bits in the DRST
 +
|-
 +
| READY || 1 || READY bit from the DRST
 +
|-
 +
| BUSY || 1 || Bus cycle in progress
 +
|-
 +
| END CYCLE || 1 || Bus cycle is complete
 +
|-
 +
| GO || 1 || GO bit from the DRST
 +
|}
  
 
==Implementation==
 
==Implementation==
  
−
It was constructed from a number of smaller [[Flip Chip]]s which were installed in custom 4-slot [[backplane]] [[system unit]]. The extant DR11-B documentation does not show either the modules used in the DR11-B, or their locations in the backplane, so that information is given here.
+
It was constructed from a number of smaller [[FLIP CHIP]]s which were installed in custom 4-slot [[system unit]] [[backplane]].
 +
 
 +
The extant DR11-B documentation does not show either the modules used in the DR11-B, or their locations in the backplane, so that information is given here.
  
 
The modules are:
 
The modules are:
Line 10: Line 100:
 
* M113 - 10 x 2-input NAND gates
 
* M113 - 10 x 2-input NAND gates
 
* M116 - 6 x 4-input NOR gates
 
* M116 - 6 x 4-input NOR gates
−
* M205 - 5 x 'D' flip flops
+
* M205 - 5 x 'D' [[flip-flop]]s
 
* 2 x M208 - 8-bit buffer / shift-register
 
* 2 x M208 - 8-bit buffer / shift-register
 
* M239 - 3 x 4-bit counter/register
 
* M239 - 3 x 4-bit counter/register
 
* 2 x M611 - High speed power inverters
 
* 2 x M611 - High speed power inverters
 
* M796 - UNIBUS Master Control
 
* M796 - UNIBUS Master Control
−
* M7821 - Interrupt Control
+
* [[M782 Interrupt Control|M7821]] - [[Interrupt]] Control
 
* M7219 - Bus Interface
 
* M7219 - Bus Interface
  
Line 38: Line 128:
 
Connection to the user device is via either a pair of M957 Split-Lug Cable boards, or via an M9760 (dual) Twisted Pair Cable Connector board. The M9680 (dual) board is a loopback test board, which can be inserted in place of the user connection board(s).
 
Connection to the user device is via either a pair of M957 Split-Lug Cable boards, or via an M9760 (dual) Twisted Pair Cable Connector board. The M9680 (dual) board is a loopback test board, which can be inserted in place of the user connection board(s).
  
−
Power comes in on a single-width stub card in the A3 slot (as is canonical in the [[PDP-11/20]] generation of PDP-11).
+
Power comes in on a single-width stub card in the A3 slot (as is canonical in the [[PDP-11/20]] generation of [[PDP-11]]s).
 +
 
 +
==Further reading==
 +
 
 +
* ''DRll-B Engineering Drawings'' - not online at this time
 +
 
 +
==External links==
  
−
{{PDP-11}}
+
* [http://www.bitsavers.org/www.computer.museum.uq.edu.au/pdf/DEC-11-HDRBA-D-D%20DR11-B&DA11-B%20Manual.pdf DR11-B/DA11-B manual] (DEC-11-HDRBA-D-D)
 +
* [http://www.bitsavers.org/pdf/dec/unibus/EK-DR11B-TM-004_DR11-B_DA11-B_Manual_Sep74.pdf DR11-B/DA11-B manual] (EK-DR11B-TM-004)
  
−
[[Category:UNIBUS Peripherals]]
+
[[Category: UNIBUS Parallel Interfaces]]

Latest revision as of 02:15, 25 November 2022

The DR11-B was a parallel interface for the UNIBUS, one which used DMA to transfer data to a user device.

The interface between the DR11-B and the user device uses a number of unidirectional control lines (below), which control data transfer; and sets of three 'status' and 'control' lines, which appear in the Status and Command Register. By appropriate manipulation of the control lines, the user device can do byte or word cycles on the bus, perform read-modify-write bus cycles, or do block 'burst' bus transfers.

Data going to the user device is buffered in a set of latches; data coming from the user device is not buffered, and must be held valid for the duration of the resultant bus cycle.

Registers

Register Abbreviation Address
Word Count Register DRWC 772410
Bus Address Register DRBA 772412
Status and Command Register DRST 772414
Data Buffer Register DRDB 772416

The addresses shown are for the first DR11-B in a system; additional ones are normally set to be at 772430, 772450, 772470, etc.

772410: Word Count Register (DRWC)

WC15 <---> WC00
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

772412: Bus Address Register (DRBA)

BA15 <---> BA00
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

772414: Status and Command Register (DRST)

ERROR NEX ATTN MAINT DSTAT A-C CYCLE READY IE XBA16-17 FNCT1-3 GO
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

772416: Data Buffer Register (DRDB)

Data15 <---> Data00
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Note: Unlike most DEC DMA devices, an overflow in the Bus Address Register does not carry into the Extended Memory bits in the CSR.

User Device Interface

User Input Signals

Signal Name Count Function
DAT IN 16 Data from user device
CONTROL 2 Specify type of UNIBUS cycle (DATI, etc)
CYCLE REQ 2 Either one can set the CYCLE bit, which causes a bus cycle
WC INC ENB 1 Word Count Increment Enable
BA INC ENB 1 Bus Address Increment Enable
A00 1 Bus Address Bit 0
DSTAT 3 Device Status Bits
ATTN 1 Attention bit in the DRST
SINGLE CYCLE 1 Controls use of burst mode for bus cycles

User Output Signals

Signal Name Count Function
DAT OUT 16 Data to user device
INITIALIZE 1 UNIBUS INIT or interlock error
FNCT 3 Function bits in the DRST
READY 1 READY bit from the DRST
BUSY 1 Bus cycle in progress
END CYCLE 1 Bus cycle is complete
GO 1 GO bit from the DRST

Implementation

It was constructed from a number of smaller FLIP CHIPs which were installed in custom 4-slot system unit backplane.

The extant DR11-B documentation does not show either the modules used in the DR11-B, or their locations in the backplane, so that information is given here.

The modules are:

  • M112 - 10 x 2-input NOR gates
  • M113 - 10 x 2-input NAND gates
  • M116 - 6 x 4-input NOR gates
  • M205 - 5 x 'D' flip-flops
  • 2 x M208 - 8-bit buffer / shift-register
  • M239 - 3 x 4-bit counter/register
  • 2 x M611 - High speed power inverters
  • M796 - UNIBUS Master Control
  • M7821 - Interrupt Control
  • M7219 - Bus Interface

The M7219 is a quad card; the others are all single. (Of those, the M796 and M7821 are extended length; the others are all standard length.) The M239 is used to hold the Command and Status Register.

Board locations (as seen from the board insertion side of the backplane, not the wire-wrap pin side, as is common in DEC documentation) are:

Connector
Slot A B C D E F
1 UNIBUS In M7219
2 Test board M208 M208 M7821 M796
3 Power M205 M611 M611 M112 M113
4 UNIBUS Out User connector M116 M239

Connection to the user device is via either a pair of M957 Split-Lug Cable boards, or via an M9760 (dual) Twisted Pair Cable Connector board. The M9680 (dual) board is a loopback test board, which can be inserted in place of the user connection board(s).

Power comes in on a single-width stub card in the A3 slot (as is canonical in the PDP-11/20 generation of PDP-11s).

Further reading

  • DRll-B Engineering Drawings - not online at this time

External links

Retrieved from "https://gunkies.org/w/index.php?title=DR11-B_parallel_interface&oldid=28200"