Difference between revisions of "MSV11-M QBUS memory"

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==Configuration==
 
==Configuration==
  
−
No documentation on the MSV11-M is extant, so it is currently not known how to configure it.<!-- A single 8-position [[Dual Inline Package|DIP]] switch configures the card:
+
No documentation on the MSV11-M is extant, so it is currently not known how to configure it. The purpose of the two-position jumper between E19 (apparently a [[delay line]]) and E18 is currently unknown.
−
* Switches S1-S2 select the 22-bit starting address;
+
<!-- A single 6-position [[Dual Inline Package|DIP]] switch configures the card's 22-bit starting address:
 
* Switches S3-S4 must always be OFF;
 
* Switches S3-S4 must always be OFF;
−
* Switches S5-S8 select the CSR address.
 
 
{| class="wikitable"
 
{| class="wikitable"
 
! S1 || S2 || Staring Address
 
! S1 || S2 || Staring Address
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|-
 
|-
 
| ON || ON || 14000000 (3 MB)
 
| ON || ON || 14000000 (3 MB)
−
|}
+
|} -->
 +
 
 
==Control Register==
 
==Control Register==
−
Each board has a single control [[register]], which can be configured in the range 17772100-17772136.
+
 
 +
Each board has a single control [[register]], which can be configured in the range 17772100-17772136, using the set of four jumpers between chips E27 and E26. They are not numbered on the board; for our purposes we will number them W1-W4, starting with the left-hand jumper, with the board oriented with the insertion handles at the top.
 +
 
 
{| class="wikitable"
 
{| class="wikitable"
−
! S5 !! S6 !! S7 !! S8 !! CSR Address
+
! W4 !! W3 !! W2 !! W1 !! CSR Address
 
|-
 
|-
−
| ON || ON || ON || ON || 17772100
+
| In || In || In || In || 17772100
 
|-
 
|-
−
| ON || ON || ON || OFF || 17772102
+
| In || In || In || Out || 17772102
 
|-
 
|-
−
| ON || ON || OFF || ON || 17772104
+
| In || In || Out || In || 17772104
 
|-
 
|-
−
| ON || ON || OFF || OFF || 17772106
+
| In || In || Out || Out || 17772106
 
|-
 
|-
−
| ON || OFF || ON || ON || 17772110
+
| In || Out || In || In || 17772110
 
|-
 
|-
−
| ON || OFF || ON || OFF || 17772112
+
| In || Out || In || Out || 17772112
 
|-
 
|-
−
| ON || OFF || OFF || ON || 17772114
+
| In || Out || Out || In || 17772114
 
|-
 
|-
−
| ON || OFF || OFF || OFF || 17772116
+
| In || Out || Out || Out || 17772116
 
|-
 
|-
−
| OFF || ON || ON || ON || 17772120
+
| Out || In || In || In || 17772120
 
|-
 
|-
−
| OFF || ON || ON || OFF || 17772122
+
| Out || In || In || Out || 17772122
 
|-
 
|-
−
| OFF || ON || OFF || ON || 17772124
+
| Out || In || Out || In || 17772124
 
|-
 
|-
−
| OFF || ON || OFF || OFF || 17772126
+
| Out || In || Out || Out || 17772126
 
|-
 
|-
−
| OFF || OFF || ON || ON || 17772130
+
| Out || Out || In || In || 17772130
 
|-
 
|-
−
| OFF || OFF || ON || OFF || 17772132
+
| Out || Out || In || Out || 17772132
 
|-
 
|-
−
| OFF || OFF || OFF || ON || 17772134
+
| Out || Out || Out || In || 17772134
 
|-
 
|-
−
| OFF || OFF || OFF || OFF || 17772136
+
| Out || Out || Out || Out || 17772136
 
|}
 
|}
−
In the register contents (below), all the bits can be read and written by [[software]]; most are cleared by power up and bus INIT. Bits which can only be modified by the CPU are shown in normal font, and those which can also be set by the [[hardware]] in ''italics''.
+
<!--In the register contents (below), all the bits can be read and written by [[software]]; most are cleared by power up and bus INIT. Bits which can only be modified by the CPU are shown in normal font, and those which can also be set by the [[hardware]] in ''italics''.
 
{{16bit-header}}
 
{{16bit-header}}
 
| ''Parity Error'' || Extended Error Address Enable || colspan=2 | Reserved || colspan=7 | ''Error Address'' || colspan=2 | Reserved || Write Wrong Parity || Reserved || Parity Error Enable  
 
| ''Parity Error'' || Extended Error Address Enable || colspan=2 | Reserved || colspan=7 | ''Error Address'' || colspan=2 | Reserved || Write Wrong Parity || Reserved || Parity Error Enable  
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==Further reading==
 
==Further reading==
  
−
* ''MSV11-M User Guide'', EK-MSV1M-UG
+
* ''MSV11-M User Guide'' (EK-MSV1M-UG - not online)
−
* ''MSV11-M Field Maintenance Printset'' (MP-02053 - not online)
+
* ''MSV11-M Field Maintenance Print Set'' (MP02053 - not online)
−
 
 
−
{{PDP-11}}
 
  
 
[[Category: QBUS Memories]]
 
[[Category: QBUS Memories]]

Latest revision as of 20:25, 2 July 2023

MSV11-MB card

The MSV11-M (M7506) is a dual-height QBUS DRAM main memory card. The MSV11-MB (M7506-BA) holds 1 MByte when fully populated with 256K DRAMs chips, the MSV11-MA (M7506-AA) is half-populated (the only partially-filled configuration allowed) and holds 512 Kbytes.

The memory is arranged as 2 banks, each 16 data bits (1 PDP-11 word) wide, with 2 additional bits for parity (1 per byte). It is a Q22 card; it reportedly supports QBUS block mode.

Configuration

No documentation on the MSV11-M is extant, so it is currently not known how to configure it. The purpose of the two-position jumper between E19 (apparently a delay line) and E18 is currently unknown.

Control Register

Each board has a single control register, which can be configured in the range 17772100-17772136, using the set of four jumpers between chips E27 and E26. They are not numbered on the board; for our purposes we will number them W1-W4, starting with the left-hand jumper, with the board oriented with the insertion handles at the top.

W4 W3 W2 W1 CSR Address
In In In In 17772100
In In In Out 17772102
In In Out In 17772104
In In Out Out 17772106
In Out In In 17772110
In Out In Out 17772112
In Out Out In 17772114
In Out Out Out 17772116
Out In In In 17772120
Out In In Out 17772122
Out In Out In 17772124
Out In Out Out 17772126
Out Out In In 17772130
Out Out In Out 17772132
Out Out Out In 17772134
Out Out Out Out 17772136

Technical information

As far as is known, there are no copies of the engineering drawings extant for the MSV11-M.

Further reading

  • MSV11-M User Guide (EK-MSV1M-UG - not online)
  • MSV11-M Field Maintenance Print Set (MP02053 - not online)
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