Difference between revisions of "PDP-8/S"
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(see "Computer Structures: Readings and Examples", page 120: "A PDP-S/S is one-fifteenth of a PDP-8 at one-half the cost. ...even though the same 2-megahertz logic clock is used in both cases.") |
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| virtual address = 4k words | | virtual address = 4k words | ||
| design type = [[clock]]ed random [[logic]] | | design type = [[clock]]ed random [[logic]] | ||
| − | | clock speed = | + | | clock speed = 1.333Mhz (per bit) |
| + | | cycle time = 10.5 μseconds (per word) | ||
| memory speed = 8 μseconds | | memory speed = 8 μseconds | ||
| memory mgmt = bank select | | memory mgmt = bank select | ||
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| successor = [[PDP-8/L]] | | successor = [[PDP-8/L]] | ||
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| year announced = | | year announced = | ||
| year design started = | | year design started = | ||
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| cpu = | | cpu = | ||
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| − | | price = US$ | + | | price = US$ |
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| − | The '''PDP-8/S''' was [[Digital Equipment Corporation|DEC]]'s attempt to produce a 'cheaper' [[PDP-8]]. It was a [[serial computer|serial]] implementation, which reduced the part count somewhat, but resulted in an incredibly slow machine, compared to the rest of the line. It was soon discontinued. | + | The '''PDP-8/S''' was [[Digital Equipment Corporation|DEC]]'s attempt to produce a 'cheaper' [[PDP-8 family|PDP-8]]. It was a [[serial computer|serial]] implementation, which reduced the part count somewhat, but resulted in an incredibly slow machine, compared to the rest of the line. It was soon discontinued. |
The PDP-8 was constructed with discrete [[transistor]]s, packaged into DEC's [[FLIP CHIP]] technology. It could perform an addition to the [[accumulator]] in 64 μseconds. It had [[parity]] on the [[main memory]] as standard, not optional. | The PDP-8 was constructed with discrete [[transistor]]s, packaged into DEC's [[FLIP CHIP]] technology. It could perform an addition to the [[accumulator]] in 64 μseconds. It had [[parity]] on the [[main memory]] as standard, not optional. | ||
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* MM8S Memory Module | * MM8S Memory Module | ||
* ME8S Memory Extension, holds two MM8S | * ME8S Memory Extension, holds two MM8S | ||
| + | |||
| + | ==Images== | ||
| + | |||
| + | [[Image:PDP-8'S_TekniskaMuseet-Stockholm,Sweden.jpg|left|thumb|400px|PDP-8/S in the Tekniska Museet in Stockholm, Sweden]] | ||
{{Nav PDP-8}} | {{Nav PDP-8}} | ||
[[Category: PDP-8s]] | [[Category: PDP-8s]] | ||
Latest revision as of 13:10, 14 July 2023
| PDP-8/S | |
 PDP-8/S front panel inlay | |
| Manufacturer: | DEC |
|---|---|
| Architecture: | PDP-8 |
| Year Introduced: | 1967 |
| Year Discontinued: | 1970 |
| Form Factor: | minicomputer |
| Word Size: | 12 bits |
| Logic Type: | DTL |
| Design Type: | clocked random logic |
| Clock Speed: | 1.333Mhz (per bit) |
| Cycle Time: | 10.5 μseconds (per word) |
| Memory Speed: | 8 μseconds |
| Physical Address Size: | 32k words (requires optional MC8S) |
| Virtual Address Size: | 4k words |
| Memory Management: | bank select |
| Bus Architecture: | Negative I/O Bus |
| Predecessor(s): | PDP-8 |
| Successor(s): | PDP-8/L |
The PDP-8/S was DEC's attempt to produce a 'cheaper' PDP-8. It was a serial implementation, which reduced the part count somewhat, but resulted in an incredibly slow machine, compared to the rest of the line. It was soon discontinued.
The PDP-8 was constructed with discrete transistors, packaged into DEC's FLIP CHIP technology. It could perform an addition to the accumulator in 64 μseconds. It had parity on the main memory as standard, not optional.
Options
Options included:
- DB8S Data Break, needed for data break on the I/O bus
- MC8S Memory Extension Control, which was needed to support more than 4k words of memory
- MM8S Memory Module
- ME8S Memory Extension, holds two MM8S
Images
| v • d • e PDP-8 Computers, Software and Peripherals |
|---|
| PDP-8s: PDP-5 • PDP-8 • LINC-8 • PDP-8/S • PDP-8/I • PDP-8/L • PDP-12 • PDP-8/E • PDP-8/F • PDP-8/M • PDP-8/A
Workstations: VT78 Also: PDP-8 family • PDP-8 architecture • PDP-8 Memory Extension units |
