Difference between revisions of "MM11-C core memory"
m (+link) |
m (interleaving cleanup) |
||
| Line 6: | Line 6: | ||
There was also a [[parity]]-capable variant, the '''MM11-CP''', which uses an [[M7850 parity controller]] plugged into the same backplane as the MM11-C, and substituted a core array with two more bits per word, the H221-A. | There was also a [[parity]]-capable variant, the '''MM11-CP''', which uses an [[M7850 parity controller]] plugged into the same backplane as the MM11-C, and substituted a core array with two more bits per word, the H221-A. | ||
| − | It is possible to [[interleave]] a pair of MM11-C's to provide reduced effective average [[access time]]s. | + | It is possible to [[memory interleaving|interleave]] a pair of MM11-C's to provide reduced effective average [[access time]]s. |
The MM11-C did not use a custom backplane; it plugged into a standard [[Modified UNIBUS Device|MUD slot]]. The pair was 'thick' enough that a normal board cannot be plugged into the next slot; instead, a [[G727 grant continuity card]] must be used there (since it has no components on it, it just clears the H221 card). | The MM11-C did not use a custom backplane; it plugged into a standard [[Modified UNIBUS Device|MUD slot]]. The pair was 'thick' enough that a normal board cannot be plugged into the next slot; instead, a [[G727 grant continuity card]] must be used there (since it has no components on it, it just clears the H221 card). | ||
Latest revision as of 23:46, 29 July 2023
The MM11-C was a 16 Kbyte core main memory for the early PDP-11 UNIBUS machines. An MM11-C was composed of two hex boards, one piggy-backed on the other, and the pair taking only a single backplane slot (electrically):
- An H221-B daughter-board containing the cores
- A G651 mother-board containing most of the electronics, and the contact fingers for plugging into a backplane.
There was also a parity-capable variant, the MM11-CP, which uses an M7850 parity controller plugged into the same backplane as the MM11-C, and substituted a core array with two more bits per word, the H221-A.
It is possible to interleave a pair of MM11-C's to provide reduced effective average access times.
The MM11-C did not use a custom backplane; it plugged into a standard MUD slot. The pair was 'thick' enough that a normal board cannot be plugged into the next slot; instead, a G727 grant continuity card must be used there (since it has no components on it, it just clears the H221 card).
Configuration
The DEC manuals for the MM11-C are not available online. Basic address configuration is by an 8-position DIP switch (in 4 groups of 2):
| Address bit | Switches |
|---|---|
| A17 | S8, S7 |
| A16 | S6, S5 |
| A15 | S4, S3 |
| A14 | S2, S1 |
The W8 and W9 jumpers (used to configure the MM11-B core memory, which also uses the G651) must both be out. Jumpers W4 through W7 replicate the functionality of S1-S8. For interleave control:
| Interleave | W0 | W1 | W2 | W3 |
|---|---|---|---|---|
| Off | In | Out | In | Out |
| On | Out | In | Out | In |
In interleaved memories, the S1 and S2 pair should be set to opposing settings in each of the two boards; i.e. both on in one, and both off on the other.
The jumpers are on the G651 board, on the center right (with the board upright, with the contact fingers at the bottom). W4-W7 are in the center group there, interspersed with resistors; W0, W1, W3 and W2 are on the left end of the right-hand group (toward the edge of the board), and W8 and W9 are on on the right end.
