MD10 core memory: Difference between revisions
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The '''MD10''' was a [[core memory|core]] [[main memory]] system for the early [[PDP-10]]s, principally the [[KA10]]. An MD10 could contain two to four 32KW memory modules, for a maximum of 128KW; [[access time]] is 0.8 μseconds, and the [[cycle time]] is a maximum of 1.8 μseconds. It connected to the so-called external memory bus of the 18-bit [[address]] form; [[parity]] is provided to protect the memory contents. | The '''MD10''' was a [[core memory|core]] [[main memory]] system for the early [[PDP-10]]s, principally the [[KA10]]. An MD10 could contain two to four 32KW memory modules, for a maximum of 128KW; [[access time]] is 0.8 μseconds, and the [[cycle time]] is a maximum of 1.8 μseconds. It connected to the so-called [[PDP-10 Memory Bus|external memory bus]] of the 18-bit [[address]] form; [[parity]] is provided to protect the memory contents. | ||
It was a [[multi-port memory]], with 4 ports per memory system: the [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s. | It was a [[multi-port memory]], with 4 ports per memory system: the [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s. | ||
Each port on each module could be independently set for its address, and for two-way [[interleaving]] (using address bits 20 and 35); each port can also be four-way interleaved (on all modules at once), using address bits 19 and 34. | Each port on each module could be independently set for its address, and for two-way [[memory interleaving|interleaving]] (using address bits 20 and 35); each port can also be four-way interleaved (on all modules at once), using address bits 19 and 34 (recall that the PDP-10 uses [[big-endian]] numbering, so bit 35 is the low-order bit). | ||
Internal interleaving (among modules in a single MD10) is not productive; the whole MD10 is tied up whenever any module is active. | Internal interleaving (among modules in a single MD10) is not productive; the whole MD10 is tied up whenever any module is active. | ||
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Each port and each module can independently be completely disabled (i.e. all modules from a single port, or all ports from a single module; but not a single module from a single port). | Each port and each module can independently be completely disabled (i.e. all modules from a single port, or all ports from a single module; but not a single module from a single port). | ||
[[Category: PDP-10 | ==See also== | ||
* [[PDP-10 memories]] | |||
[[Category: PDP-10 Memories]] | |||
Latest revision as of 11:54, 2 August 2023
The MD10 was a core main memory system for the early PDP-10s, principally the KA10. An MD10 could contain two to four 32KW memory modules, for a maximum of 128KW; access time is 0.8 μseconds, and the cycle time is a maximum of 1.8 μseconds. It connected to the so-called external memory bus of the 18-bit address form; parity is provided to protect the memory contents.
It was a multi-port memory, with 4 ports per memory system: the CPU uses one port (in a multi-processor system, one per CPU); the others are used by channels (such as a DF10) for mass storage such as disks.
Each port on each module could be independently set for its address, and for two-way interleaving (using address bits 20 and 35); each port can also be four-way interleaved (on all modules at once), using address bits 19 and 34 (recall that the PDP-10 uses big-endian numbering, so bit 35 is the low-order bit).
Internal interleaving (among modules in a single MD10) is not productive; the whole MD10 is tied up whenever any module is active.
Each port and each module can independently be completely disabled (i.e. all modules from a single port, or all ports from a single module; but not a single module from a single port).
