PDP-10 Memory Bus

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Memory bus Quick Latch connector (in latched position)

The PDP-10 Memory Bus, the main memory bus of the PDP-10, existed in three generations. (There were likewise three generations of memory systems to attach to them.)

The first two were the so-called 'external memory bus', in KA (18-bit address) and KI (22-bit) forms (for the KA10, and KI10 and early KL10, respectively), although they also had minor protocol differences.

The last was the 'internal memory bus', the S-Bus; for the later KL10s, a later version of the S-Bus, the X-Bus, used with MOS 'internal' memory, differed only in the logic family it interfaced to. They perform memory transfers in blocks of up to four words, so that four words can be read in any cycle; the block can start with any word within the block. The KL10 contains a pair of S-Busses, designated 0 and 1.

The differences between the two external bus types required a KI10-M Memory Bus Adapter if KA-type units were to be attached to a KI10. Similarly, KI-type units could be attached to the S-Bus using a DMA20 Memory Bus Adapter.

For DMA, mass storage peripherals connected directly to memories (PDP-10 memories are generally multi-port).

Physical form

On the KA10, all the busses were physically instantiated as cables with a pair of dual width PCBs at each end, which plugged into slots in a standard DEC backplane; these later became the CJ connectors.

On the KI10, and KL10s with an external memory bus, the memory bus cables ended in a large QuickLatch connector; these connectors were also used on the CPU end of I/O bus cables of those machines.

See also

External links

  • EK-108OU-PD-002, "KL10-Based Physical Description" - has images of CJ dual card connectors and QuickLatch connectors, pp. 69-70