Difference between revisions of "S-1 supercomputer"

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The S-1 was a supercomputer architecture jointly developed by Stanford University and Lawrence Livermore National Laboratory. The architecture was inspired by the [[PDP-10]]; among other things the word size was 36 bits.
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The '''S-1''' was a [[supercomputer]] architecture jointly developed by [[Stanford University]] and [[Lawrence Livermore National Laboratory]]. It was [[MIMD]] [[multi-processor]] using [[shared memory]], all units connected through a [[crossbar]] switch, similar to [[C.mmp]].
  
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Five generations was planned, but only two were built the Mark I, and the Mark IIA.
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Five generations was planned; the uni-processor first generation was intended to have about the processing power of a [[CDC 7600]], but in actuality fell short of that. It was intended that each [[Central Processing Unit|processor]] in a full 16-processor system in the second-generation design would have about the processing power of a [[Cray 1]].
  
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[[Common Lisp]] got many number crunching features from S-1 Lisp.
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Each processor had a [[cache]], but coherence between caches was partially in software - one processor could be notified by hardware, on attempting to utilize a given location, that another processor was currently authoritative for that location, and it would have to request that the other processor flush its cache of that location. That communication was to be via what was effectively a [[local area network|LAN]] which ran to all the processors. That LAN was to be a [[bus]] (similar to an [[Ethernet]]) in the initial implementation; it was planned to use a [[slotted ring]] in the later generations.
  
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Single instances of only the first two generations, the Mark I, and the Mark IIA, were built. Both were [[wire-wrap]]ped, and implemented in [[emitter-coupled logic|ECL]]. The Mark IIA was actually implemented with the help of design tools, including an advanced [[circuit]] [[simulator]], which ran on the Mark I.
  
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[[Category: Mainframes]]
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The architecture was inspired by the [[PDP-10]], but added support for [[segment]]ation; among other things, the [[word]] size was 36 bits. The [[operating system]] planned for the machine, [[Amber]], was heavily based on [[Multics]]. [[Common Lisp]] got many number crunching features from S-1 [[LISP]].
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==External links==
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* [http://bitsavers.org/pdf/llnl/s1/ S1]
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** [http://bitsavers.org/pdf/llnl/s1/S1_MKIIA_Article_Sep79.pdf The S-1 Project]
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* [http://www.bitsavers.org/pdf/stanford/cs_techReports/STAN-CS-79-715_S-1_Arch_Man.pdf S-1 Architecture Manual] (STAN-CS-79-715)
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* [https://www.osti.gov/servlets/purl/5991007 The S-1 Project - 1979 Annual Report: Volume I - Architecture]
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* [https://www.osti.gov/servlets/purl/5921576 The S-1 Project - 1979 Annual Report: Volume II - Hardware]<!-- https://digital.library.unt.edu/ark:/67531/metadc1103174/ -->
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* [https://www.osti.gov/biblio/6129807 The S-1 Project - 1979 Annual Report: Volume III - Software]
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* [http://www.mit.edu/~cbf/thesis.htm The Amber Operating System]
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* [http://www-forum.stanford.edu/wiki/index.php/S-1_project S-1 project]
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* [http://infolab.stanford.edu/pub/voy/museum/pictures/S-1.html The Lawrence Livermore Laboratory S-1 project and Stanford University]
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** [http://infolab.stanford.edu/pub/voy/museum/pictures/S-1/hardware.html Photographs of the S-1 computers]
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** [http://infolab.stanford.edu/pub/voy/museum/pictures/S-1/CHM.html Photographs of the S-1 Mark I at the CHM warehouse]
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* [https://people.computing.clemson.edu/~mark/s1.html S-1 Supercomputer (1975-1988)]
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[[Category: Supercomputers]]
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[[Category: 36-bit Computers]]
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[[Category: Unique Computers]]

Latest revision as of 19:31, 1 March 2024

The S-1 was a supercomputer architecture jointly developed by Stanford University and Lawrence Livermore National Laboratory. It was MIMD multi-processor using shared memory, all units connected through a crossbar switch, similar to C.mmp.

Five generations was planned; the uni-processor first generation was intended to have about the processing power of a CDC 7600, but in actuality fell short of that. It was intended that each processor in a full 16-processor system in the second-generation design would have about the processing power of a Cray 1.

Each processor had a cache, but coherence between caches was partially in software - one processor could be notified by hardware, on attempting to utilize a given location, that another processor was currently authoritative for that location, and it would have to request that the other processor flush its cache of that location. That communication was to be via what was effectively a LAN which ran to all the processors. That LAN was to be a bus (similar to an Ethernet) in the initial implementation; it was planned to use a slotted ring in the later generations.

Single instances of only the first two generations, the Mark I, and the Mark IIA, were built. Both were wire-wrapped, and implemented in ECL. The Mark IIA was actually implemented with the help of design tools, including an advanced circuit simulator, which ran on the Mark I.

The architecture was inspired by the PDP-10, but added support for segmentation; among other things, the word size was 36 bits. The operating system planned for the machine, Amber, was heavily based on Multics. Common Lisp got many number crunching features from S-1 LISP.

External links

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