S-1 supercomputer

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The S-1 was a supercomputer architecture jointly developed by Stanford University and Lawrence Livermore National Laboratory. It was MIMD multi-processor using shared memory, all units connected through a crossbar switch, similar to C.mmp.

Five generations was planned; the uni-processor first generation was intended to have about the processing power of a CDC 7600, but in actuality fell short of that. It was intended that each processor in a full 16-processor system in the second-generation design would have about the processing power of a Cray 1.

Each processor had a cache, but coherence between caches was partially in software - one processor could be notified by hardware, on attempting to utilize a given location, that another processor was currently authoritative for that location, and it would have to request that the other processor flush its cache of that location. That communication was to be via what was effectively a LAN which ran to all the processors. That LAN was to be a bus (similar to an Ethernet) in the initial implementation; it was planned to use a slotted ring in the later generations.

Single instances of only the first two generations, the Mark I, and the Mark IIA, were built. Both were wire-wrapped, and implemented in ECL. The Mark IIA was actually implemented with the help of design tools, including an advanced circuit simulator, which ran on the Mark I.

The architecture was inspired by the PDP-10, but added support for segmentation; among other things, the word size was 36 bits. The operating system planned for the machine, Amber, was heavily based on Multics. Common Lisp got many number crunching features from S-1 LISP.

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