Difference between revisions of "Chaosnet interface"

From Computer History Wiki
Jump to: navigation, search
(Add registers)
m (Move to new sub-cat)
 
(3 intermediate revisions by 2 users not shown)
Line 8: Line 8:
 
I am not certain of this; I think cards with pins on the back did this, which is why they made card with pins on the package side. -->
 
I am not certain of this; I think cards with pins on the back did this, which is why they made card with pins on the package side. -->
  
−
Their [[bus]] [[address]] and [[interrupt vector]]s can be set via [[Dual Inline Package|DIP]] switches; <!-- to 7mnnp0 for the address (where m can be 6 or 7, and p 0,2,4 or 6), and 0xx0 for the vector. --> the default is 0764140<!-- and 0340 -->. The [[network address]] is also set via a DIP switch.
+
Their [[bus]] [[address]] and [[interrupt vector]]s can be set via [[Dual Inline Package|DIP]] switches; <!-- to 7mnnp0 for the address (where m can be 6 or 7, and p 0,2,4 or 6), and 0xx0 for the vector. --> the defaults are 0764140 and 0270. The [[network address]] is also set via a DIP switch.
  
 
==Device registers==
 
==Device registers==
Line 71: Line 71:
 
| RCL || Receiver clear
 
| RCL || Receiver clear
 
|-
 
|-
−
| SPY || Spy - accept any messages
+
| SPY || Accept all messages
 
|-
 
|-
 
| LPBK || Loop back in interface
 
| LPBK || Loop back in interface
Line 87: Line 87:
 
===764142: Write Buffer Register (WBF)===
 
===764142: Write Buffer Register (WBF)===
 
{{16bit-header}}
 
{{16bit-header}}
−
| colspan=16 | '''OutData15 <--- OutData00'''
+
| colspan=16 | '''OutData15 <---> OutData00'''
 
{{16bitoctal-bitout}}
 
{{16bitoctal-bitout}}
  
Line 95: Line 95:
  
 
{{16bit-header}}
 
{{16bit-header}}
−
| colspan=16 | ''InData15 <--- InData0''
+
| colspan=16 | ''InData15 <---> InData0''
 
{{16bitoctal-bitout}}
 
{{16bitoctal-bitout}}
  
Line 103: Line 103:
  
 
{{16bit-header}}
 
{{16bit-header}}
−
| colspan=4 | Unused || colspan=12 | ''BitCount11 <--- BitCount0''
+
| colspan=4 | Unused || colspan=12 | ''BitCount11 <---> BitCount0''
 
{{16bitoctal-bitout}}
 
{{16bitoctal-bitout}}
  
−
Read-only register.
+
On the Chaosnet UNIBUS interface, a read-only register.
 +
 
 +
On the QBCHNI, ''writing'' the interface's network address into this register initiates transmission of a packet.
 +
 
 +
===764152: Initiate Transmission Register (XMT)===
 +
{{16bit-header}}
 +
| colspan=8 | ''Subnet7 <---> Subnet0'' || colspan=8 | ''Host7 <---> Host0''
 +
{{16bitoctal-bitout}}
 +
 
 +
On the Chaosnet UNIBUS interface, a read-only register; ''reading'' it initiates transmission of a packet. (The data returned is the interface's network address.)
 +
 
 +
===764160: Load Interval Timer Register (TIM)===
 +
{{16bit-header}}
 +
| colspan=16 | '''Timer15 <---> Timer00'''
 +
{{16bitoctal-bitout}}
 +
 
 +
Write-only register.
  
 
==External links ==
 
==External links ==
Line 121: Line 137:
 
[[Category: UNIBUS Network Interfaces]]
 
[[Category: UNIBUS Network Interfaces]]
 
[[Category: QBUS Network Interfaces]]
 
[[Category: QBUS Network Interfaces]]
 +
[[Category: Chaosnet Hardware]]

Latest revision as of 22:32, 1 August 2024

CH11 Unibus board

The Chaosnet UNIBUS interface (also called the CHAOS-11, CH11, QUAD and QAD; there was no generally-used name) and QBCHNI are Chaosnet network interfaces, for the UNIBUS and QBUS respectively. (The two device controllers are identical in programming terms, so they are both covered in this single article.)

They use programmed I/O to transfer data to and from buffers in main memory. They have on-board buffers (one each for inbound and outbound) which can hold one packet of data.

They are both a single quad wire-wrapped card.

Their bus address and interrupt vectors can be set via DIP switches; the defaults are 0764140 and 0270. The network address is also set via a DIP switch.

Device registers

They have 7 registers:

Register Abbreviation Address
Command and Status Register CAICSR 764140
My address (read only) CAIMYN 764142
Write buffer (write only) CAIWBF 764142
Read buffer CAIRBF 764144
Read bit counter CAIRBC 764146
Unused   764150
Initiate transmission CAIXMT 764152
Unused   764154
Unused   764156
Load interval timer (write only) CAITIM 764160


In the register contents (below), bits which are read/write or unused are shown in normal font, those which are read-only are in italics, and those which are write-only are shown in bold.

764140: Control Status Register (CSR)

RDN ERR RST LSTCN TCL TDN TAB TEN REN RCL SPY LPBK TIE
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Bits are:

Bits Use
RDN Receive done
ERR CRC error
RST I/O reset for interface
LSTCN Count of messages lost
TCL Receiver clear
TDN Transmitter done
TAB Transmit aborted by conflict
TEN Transmit interrupt enable
REN Receive interrupt enable
RCL Receiver clear
SPY Accept all messages
LPBK Loop back in interface
TIE Timer interrupt enable
(was Transmitter busy)

764142: My Address Register (MYN)

Subnet7 <---> Subnet0 Host7 <---> Host0
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Read-only register.

764142: Write Buffer Register (WBF)

OutData15 <---> OutData00
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Write-only register.

764144: Read Buffer Register (RBF)

InData15 <---> InData0
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Read-only register.

764146: Read Bit Counter Register (RBC)

Unused BitCount11 <---> BitCount0
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

On the Chaosnet UNIBUS interface, a read-only register.

On the QBCHNI, writing the interface's network address into this register initiates transmission of a packet.

764152: Initiate Transmission Register (XMT)

Subnet7 <---> Subnet0 Host7 <---> Host0
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

On the Chaosnet UNIBUS interface, a read-only register; reading it initiates transmission of a packet. (The data returned is the interface's network address.)

764160: Load Interval Timer Register (TIM)

Timer15 <---> Timer00
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Write-only register.

External links

Retrieved from "https://gunkies.org/w/index.php?title=Chaosnet_interface&oldid=35003"