Difference between revisions of "Chaosnet interface"

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m (Jnc moved page QBCHNI to Chaosnet interface: QBUS and UNIBUS interfaces are very similar, will cover on the same page)
m (→‎764140: Control Status Register (CSR): Typo)
 
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The '''QBCHNI''' is a [[QBUS]] card with a [[CHAOSnet]] interface.
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[[Image:CH11-board.png|thumb|right|250px|CH11 Unibus board]]
  
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== External Links ==
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The '''Chaosnet UNIBUS interface''' (also called the '''CHAOS-11''', '''CH11''', '''QUAD''' and '''QAD'''; there was no generally-used name) and '''QBCHNI''' are [[Chaosnet]] [[network interface]]s, for the [[UNIBUS]] and [[QBUS]] respectively. (The two [[device controller]]s are identical in [[program]]ming terms, so they are both covered in this single article.)
  
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* [https://github.com/hanshuebner/cadr2/blob/master/mit/chaos/quad.setup "how to setup ... QBCHNI Chaosnet Interfaces (the LSI-11 Q-Bus version)"]
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They use [[programmed I/O]] to transfer data to and from [[buffer]]s in [[main memory]]. They have on-board buffers (one each for inbound and outbound) which can hold one [[packet]] of data.
  
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{{stub}}
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They are both a single [[DEC card form factor|quad]] [[wire-wrap]]ped card. <!-- They therefore take up two slots; a [[grant continuity card]] is required, to plug into the second slot, to carry the QBUS' [[bus grant line]]s through the second slot, if there are any devices down-bus from them.
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I am not certain of this; I think cards with pins on the back did this, which is why they made card with pins on the package side. -->
  
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Their [[bus]] [[address]] and [[interrupt vector]]s can be set via [[Dual Inline Package|DIP]] switches; <!-- to 7mnnp0 for the address (where m can be 6 or 7, and p 0,2,4 or 6), and 0xx0 for the vector. --> the defaults are 0764140 and 0270. The [[network address]] is also set via a DIP switch.
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==Device registers==
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They have 7 [[register]]s:
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{| border=1
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! Register !! Abbreviation !! Address
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|-
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|Command and Status Register      || CAICSR || 764140
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|-
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|My address (read only)            || CAIMYN || 764142
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|-
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|Write buffer (write only)        || CAIWBF || 764142
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|-
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|Read buffer                      || CAIRBF || 764144
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|-
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|Read bit counter                  || CAIRBC || 764146
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|-
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|Unused                            || &nbsp; || 764150
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|-
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|Initiate transmission            || CAIXMT || 764152
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|-
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|Unused                            || &nbsp; || 764154
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|-
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|Unused                            || &nbsp; || 764156
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|-
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|Load interval timer (write only)  || CAITIM || 764160
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|}
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In the register contents (below), bits which are read/write or unused are shown in normal font, those which are read-only are in ''italics'', and those which are write-only are shown in '''bold'''.
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===764140: Control Status Register (CSR)===
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{{16bit-header}}
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| RDN || ''ERR'' || '''RST''' || colspan=4 | ''LSTCN'' || '''TCL''' || TDN || ''TAB'' || TEN || REN || '''RCL''' || SPY || LPBK || TIE
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{{16bitoctal-bitout}}
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Bits are:
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{| class="wikitable"
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! Bits !! Use
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|-
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| RDN || Receive done
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|-
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| ERR || [[Cyclic redundancy check|CRC]] error
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|-
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| RST || I/O reset for interface
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|-
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| LSTCN || Count of messages lost
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|-
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| TCL || Transmitter clear
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|-
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| TDN || Transmitter done
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|-
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| TAB || Transmit aborted by conflict
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|-
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| TEN || Transmit interrupt enable
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|-
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| REN || Receive interrupt enable
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|-
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| RCL || Receiver clear
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|-
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| SPY || Accept all messages
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|-
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| LPBK || Loop back in interface
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|-
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| TIE || Timer interrupt enable<br>(was Transmitter busy)
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|}
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===764142: My Address Register (MYN)===
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{{16bit-header}}
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| colspan=8 | ''Subnet7 <---> Subnet0'' || colspan=8 | ''Host7 <---> Host0''
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{{16bitoctal-bitout}}
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Read-only register.
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===764142: Write Buffer Register (WBF)===
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{{16bit-header}}
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| colspan=16 | '''OutData15 <---> OutData00'''
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{{16bitoctal-bitout}}
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Write-only register.
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===764144: Read Buffer Register (RBF)===
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{{16bit-header}}
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| colspan=16 | ''InData15 <---> InData0''
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{{16bitoctal-bitout}}
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Read-only register.
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===764146: Read Bit Counter Register (RBC)===
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{{16bit-header}}
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| colspan=4 | Unused || colspan=12 | ''BitCount11 <---> BitCount0''
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{{16bitoctal-bitout}}
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On the Chaosnet UNIBUS interface, a read-only register.
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On the QBCHNI, ''writing'' the interface's network address into this register initiates transmission of a packet.
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===764152: Initiate Transmission Register (XMT)===
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{{16bit-header}}
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| colspan=8 | ''Subnet7 <---> Subnet0'' || colspan=8 | ''Host7 <---> Host0''
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{{16bitoctal-bitout}}
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On the Chaosnet UNIBUS interface, a read-only register; ''reading'' it initiates transmission of a packet. (The data returned is the interface's network address.)
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===764160: Load Interval Timer Register (TIM)===
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{{16bit-header}}
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| colspan=16 | '''Timer15 <---> Timer00'''
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{{16bitoctal-bitout}}
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Write-only register.
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==External links ==
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<!-- * [https://github.com/hanshuebner/cadr2/blob/master/mit/chaos/quad.setup "how to setup ... QBCHNI Chaosnet Interfaces (the LSI-11 Q-Bus version)"]  dup of one below -->
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* [https://github.com/PDP-10/its-vault/tree/master/files/chaos CHAOS;] - includes drawings and documentation
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** [https://github.com/PDP-10/its-vault/blob/master/files/chaos/chs.defs CHS DEFS] - register declarations
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** [https://github.com/PDP-10/its-vault/blob/master/files/chaos/%24quad.log $QUAD LOG] - "Log of ChaosNet Interface Boards (quad-high, PDP-11 version)"
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** [https://github.com/PDP-10/its-vault/blob/master/files/chaos/quad.setup QUAD SETUP] - "how to setup .. Chaosnet Interfaces"
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** [https://github.com/PDP-10/its-vault/blob/master/files/chaos/quad.eco QUAD ECO] - "ECO to .. Change cable speed to 4 MHz"
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** [https://github.com/PDP-10/its-vault/blob/master/files/chaos/qadchs.note QADCHS NOTE] - random jottings
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* [https://github.com/larsbrinkhoff/chaos-schematics/tree/master/converted SUDS drawings converted to PNG pictures]
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[[Category: UNIBUS Network Interfaces]]
 
[[Category: QBUS Network Interfaces]]
 
[[Category: QBUS Network Interfaces]]
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[[Category: Chaosnet Hardware]]

Latest revision as of 19:59, 24 November 2024

CH11 Unibus board

The Chaosnet UNIBUS interface (also called the CHAOS-11, CH11, QUAD and QAD; there was no generally-used name) and QBCHNI are Chaosnet network interfaces, for the UNIBUS and QBUS respectively. (The two device controllers are identical in programming terms, so they are both covered in this single article.)

They use programmed I/O to transfer data to and from buffers in main memory. They have on-board buffers (one each for inbound and outbound) which can hold one packet of data.

They are both a single quad wire-wrapped card.

Their bus address and interrupt vectors can be set via DIP switches; the defaults are 0764140 and 0270. The network address is also set via a DIP switch.

Device registers

They have 7 registers:

Register Abbreviation Address
Command and Status Register CAICSR 764140
My address (read only) CAIMYN 764142
Write buffer (write only) CAIWBF 764142
Read buffer CAIRBF 764144
Read bit counter CAIRBC 764146
Unused   764150
Initiate transmission CAIXMT 764152
Unused   764154
Unused   764156
Load interval timer (write only) CAITIM 764160


In the register contents (below), bits which are read/write or unused are shown in normal font, those which are read-only are in italics, and those which are write-only are shown in bold.

764140: Control Status Register (CSR)

RDN ERR RST LSTCN TCL TDN TAB TEN REN RCL SPY LPBK TIE
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Bits are:

Bits Use
RDN Receive done
ERR CRC error
RST I/O reset for interface
LSTCN Count of messages lost
TCL Transmitter clear
TDN Transmitter done
TAB Transmit aborted by conflict
TEN Transmit interrupt enable
REN Receive interrupt enable
RCL Receiver clear
SPY Accept all messages
LPBK Loop back in interface
TIE Timer interrupt enable
(was Transmitter busy)

764142: My Address Register (MYN)

Subnet7 <---> Subnet0 Host7 <---> Host0
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Read-only register.

764142: Write Buffer Register (WBF)

OutData15 <---> OutData00
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Write-only register.

764144: Read Buffer Register (RBF)

InData15 <---> InData0
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Read-only register.

764146: Read Bit Counter Register (RBC)

Unused BitCount11 <---> BitCount0
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

On the Chaosnet UNIBUS interface, a read-only register.

On the QBCHNI, writing the interface's network address into this register initiates transmission of a packet.

764152: Initiate Transmission Register (XMT)

Subnet7 <---> Subnet0 Host7 <---> Host0
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

On the Chaosnet UNIBUS interface, a read-only register; reading it initiates transmission of a packet. (The data returned is the interface's network address.)

764160: Load Interval Timer Register (TIM)

Timer15 <---> Timer00
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Write-only register.

External links

Retrieved from "https://gunkies.org/w/index.php?title=Chaosnet_interface&oldid=35584"