Difference between revisions of "Power 6/32"

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[[Image:Young-sherlock-holmes-knight.jpeg|thumb|right|3D rendering by a Power 6/32 in Young Sherlock Holmes]]
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The '''Power 6/32''', code named '''Tahoe''', from [[Computer Consoles Incorporated]], was a [[supermini]]; it used the [[VERSAbus]] as its [[bus]]. It is most noted from the [[Computer Systems Research Group|CSRG]] [[software port|porting]] [[4.3 BSD]] to it, in the [[4.3 BSD Tahoe]] release.
 +
 
 +
Although it was not very successful commercially (in part because CCI exited the computer business shortly after it was released), it was very influential as the first non-[[VAX]] machine that [[BSD]] [[UNIX]] was ported to. The Tahoe did help separate out a lot of VAX-specific code from the base, allowing BSD to become more portable, but the Power 6/32 machine quickly disappeared off the market, and not much is known about them.
 +
 
 +
The [[Central Processing Unit|CPU]] was re-sold (under other names) in systems from several vendors (viewed by CCI as [[Original Equipment Manufacturer|OEMs]]): [[Unisys]] sold the 6/32 under the name 'Unisys 7000/40', using their own bastardized BSD+SYSV Unix. (Kuwait Petroleum in Denmark had one of them.) [[ICL]] had the 'Clan 7'. [[Harris]] had the HCX-5, -7, and -9 models (for which a small amount of information survives - below), running the [[UNIX System V|SysV]] derivative HCX/UX.
 +
 
 +
Pixar used a Power 6/32 to render the stained-glass knight in the 1985 movie ''Young Sherlock Holmes''.
 +
 
 +
==Details==
 +
 
 +
The Power 6/32 CPU was implemented in [[transistor-transistor logic|TTL]]; it had a [[clock rate]] of 100nS.
 +
 
 +
The performance is given in this table, from dhrystone.c (below):
 +
<pre>
 +
*----------------DHRYSTONE VERSION 1.0 RESULTS BEGIN--------------------------
 +
*
 +
* MACHINE      MICROPROCESSOR  OPERATING      COMPILER        DHRYSTONES/SEC.
 +
* TYPE                        SYSTEM                          NO REG  REGS
 +
* --------------------------  ------------    -----------    ---------------
 +
* CCI POWER 6/32              COS(SV+4.2)    cc              7500    7800
 +
* CCI POWER 6/32              POWER 6 UNIX/V  cc              8236    8498
 +
* CCI POWER 6/32              4.2 Rel. 1.2b  cc              8963    9544
 +
* VAX 11/780  -              UNIX 5.2        cc              1515    1562
 +
* VAX 11/780  -              UNIX 4.3bsd    cc              1646    1662
 +
</pre>
 +
 
 +
Which may give some indication on the initial reasons why the Power 6/32 was chosen as the successor to the VAX by CSRG.
 +
 
 +
==Instruction Set==
 +
 
 +
Although apparently no documentation survives and is accessible, we can infer a lot from the [[instruction]] decoding/printing routines in the [[debugger]]s from 4.3 BSD Tahoe, and their input file 'instrs' (below).
 +
 
 +
* Instructions start with a 1-byte [[operation code|opcode]], and, depending on the opcode and 'addressing mode' (below), are followed by a basic set of 0-3 [[operand]]s. (Two instructions, 'ediv' and 'emul', take 4 operands; if any operand uses the 'indexed' addressing mode, an extra operand is required for each such use.)
 +
* Operands start with 1 byte, containing 4 bits of 'addressing mode' and 4 bits of '[[register]]':
 +
** The CPU has sixteen 32-bit registers r0 ... r13 ([[stack frame|fp]]), r14 ([[Stack Pointer|sp]]), r15 ([[Program Counter|pc]]).
 +
** The addressing modes (reminiscent of those of the [[PDP-11 architecture#Addressing modes|PDP-11]]), and their encodings, are:
 +
 
 +
:: {| class="wikitable"
 +
! Encoding || Mode || notation
 +
|-
 +
| 0x0 || short literals 0-15 || rowspan="4" | &nbsp;
 +
|-
 +
| 0x1 || short literals 16-31
 +
|-
 +
| 0x2 || short literals 32-47
 +
|-
 +
| 0x3 || short literals 48-63
 +
|-
 +
| 0x4 || indexed || [r]
 +
|-
 +
| 0x5 || register immediate || r
 +
|-
 +
| 0x6 || register deferred || (r)
 +
|-
 +
| 0x7 || auto-decrement || -(r)
 +
|-
 +
| 0x8 || auto-increment || (r)+
 +
|-
 +
| 0x9 || auto-increment deferred || *(r)+
 +
|-
 +
| 0xA || byte displacement || BD(r)
 +
|-
 +
| 0xB || byte displacement deferred || *BD(r)
 +
|-
 +
| 0xC || short-word displacement || WD(r)
 +
|-
 +
| 0xD || short-word displacement deferred || *WD(r)
 +
|-
 +
| 0xE || long-word displacement || LD(r)
 +
|-
 +
| 0xF || long-word displacement deferred ||*LD(r)
 +
|}
 +
 
 +
:: The "indexed" mode apparently adds the contents of the named register to the [[address]] generated by the following operand. (It likely cannot be used with the "register immediate" addressing mode.)
 +
 
 +
: For operands of the 6 'displacement' modes, the operand is followed by a value of the indicated length.
 +
 +
===Opcode table===
 +
 
 +
The opcode map and mnemonics for the [[assembly language|assembler]] are as follows:
 +
 
 +
{| class="wikitable"
 +
!  || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || a || b || c || d || e ||f
 +
|-
 +
! 0x00
 +
| halt    || -      || -      || -      || -      || sinf    || ldf    || ldd    || addb2  || movb    || addw2  || movw    || addl2  || movl    || bbs    || -     
 +
|-
 +
! 0x10
 +
| nop    || brb    || -      || brw    || -      || cosf    || lnf    || lnd    || addb3  || cmpb    || addw3  || cmpw    || addl3  || cmpl    || bbc    || -     
 +
|-
 +
! 0x20
 +
| rei    || bneq/bnequ || -      || cvtwl  || -      || atanf  || stf    || std    || subb2  || mcomb  || subw2  || mcomw  || subl2  || mcoml  || emul    || aoblss
 +
|-
 +
! 0x30
 +
| bpt    || beql/beqlu || -      || cvtwb  || -      || logf    || cmpf    || cmpd    || subb3  || bitb    || subw3  || bitw    || subl3  || bitl    || ediv    || aobleq
 +
|-
 +
! 0x40
 +
| ret    || bgtr    || -      || -      || -      || sqrtf  || cmpf2  || cmpd2  || shll    || clrb    || shlq    || clrw    || mull2  || clrl    || shal    || -     
 +
|-
 +
! 0x50
 +
| -      || bleq    || -      || -      || -      || expf    || tstf    || tstd    || shrl    || tstb    || shrq    || tstw    || mull3  || tstl    || shar    || bbssi 
 +
|-
 +
! 0x60
 +
| ldpctx  || -      || -      || -      || -      || -      || -      || pushd  || -      || incb    || -      || incw    || divl2  || incl    || -      || cvtlb 
 +
|-
 +
! 0x70
 +
| svpctx  || jmp    || -      || -      || -      || -      || cvlf    || cvld    || -      || decb    || -      || decw    || divl3  || decl    || -      || cvtlw 
 +
|-
 +
! 0x80
 +
| -      || bgeq    || movs2  || -      || -      || -      || cvfl    || cvdl    || orb2    || cvtbl  || orw2    || bispsw  || orl2    || adwc    || adda    || -     
 +
|-
 +
! 0x90
 +
| -      || blss    || cmps2  || -      || -      || -      || -      || ldfd    || orb3    || cvtbw  || orw3    || bicpsw  || orl3    || sbwc    || suba    || -     
 +
|-
 +
! 0xa0
 +
| -      || bgtru  || -      || -      || -      || -      || cvdf    || -      || andb2  || movzbl  || andw2  || loadr  || andl2  || mtpr    || ffs    || -     
 +
|-
 +
! 0xb0
 +
| -      || blequ  || -      || -      || -      || -      || negf    || negd    || andb3  || movzbw  || andw3  || storer  || andl3  || mfpr    || ffc    || calls 
 +
|-
 +
! 0xc0
 +
| prober  || bvc    || movs3  || movzwl  || -      || -      || addf    || addd    || xorb2  || movob  || xorw2  || movow  || xorl2  || movpsl  || btcs    || kcall 
 +
|-
 +
! 0xd0
 +
| probew  || bvs    || cmps3  || -      || -      || -      || subf    || subd    || xorb3  || pushb  || xorw3  || pushw  || xorl3  || pushl  || -      || -     
 +
|-
 +
! 0xe0
 +
| insque  || bgequ/bcs || -      || -      || -      || -      || mulf    || muld    || mnegb  || movab  || mnegw  || movaw  || mnegl  || moval  || -      || -     
 +
|-
 +
! 0xf0
 +
| remque  || bcc/blssu || -      || -      || -      || -      || divf    || divd    || movblk  || pushab  || -      || pushaw  || casel  || pushal || callf  || -
 +
|}
 +
 
 +
A number of the more complex arithmetic instructions, many of them the [[floating point]] and the trigonometric ones (CVLF, CVLD, CVFL, CVDL, LDFD, CVDF, ADDF, ADDD, SUBF, SUBD, MULF, MULD, DIVF, DIVD, SINF, COSF, ATANF, LOGF, SQRTF and EXPF), do not seem to be implemented in the Power 6/32; instead, they were [[emulation|emulated]] in [[software]], after an attempt to execute them resulted in a [[trap]].
 +
 
 +
{{semi-stub}}
 +
 
 +
==See also==
 +
 
 +
* [[Harris CX series]]
 +
 
 +
==External links==
 +
 
 +
* [https://virtuallyfun.com/wp-content/uploads/2017/02/harris_hcx5.jpg Harris HCX-5] - ad
 +
* [https://virtuallyfun.com/wp-content/uploads/2017/02/Harris-HCX-9-print-ad.jpg Harris HCX-9] - ad
 +
* [https://virtuallyfun.com/2017/02/24/the-harris-hcx-9-aka-tahoe-platform/ The Harris HCX-9 aka TAHOE platform]
 +
* [https://www.tuhs.org/cgi-bin/utree.pl?file=4.3BSD-Reno/src/share/doc/smm/01.setup/tahoe/ Installing and Operating 4.3BSD UNIX on the Tahoe]
 +
* [https://www.tuhs.org/cgi-bin/utree.pl?file=4.3BSD-Tahoe/usr/src/bin/adb adb] - debugger source
 +
* [https://www.tuhs.org/cgi-bin/utree.pl?file=4.3BSD-Tahoe/usr/src/ucb/dbx/ dbx]
 +
* [https://www.tuhs.org/cgi-bin/utree.pl?file=4.3BSD-Tahoe/usr/src/bin/as/as.tahoe/instrs instrs] - basic instruction table
 +
** [https://www.tuhs.org/cgi-bin/utree.pl?file=4.3BSD-Tahoe/usr/src/bin/adb/adb.tahoe/instrs instrs] - alphabetical list
 +
* [https://web.archive.org/web/20150123191735/http://www.dunnington.u-net.com/public/dhrystone.c dhrystone.c]
 +
* Cook, Carpenter, Catmull 1987 "The Reyes Image Rendering Architecture" in ACM ''Computer Graphics'' Vol. 21, No. 4 [http://dl.acm.org/citation.cfm?id=37414 PDF] indicating this machine was used at Pixar for a number of films
 +
 
 +
[[Category: Superminis]]

Revision as of 01:11, 24 December 2024

3D rendering by a Power 6/32 in Young Sherlock Holmes

The Power 6/32, code named Tahoe, from Computer Consoles Incorporated, was a supermini; it used the VERSAbus as its bus. It is most noted from the CSRG porting 4.3 BSD to it, in the 4.3 BSD Tahoe release.

Although it was not very successful commercially (in part because CCI exited the computer business shortly after it was released), it was very influential as the first non-VAX machine that BSD UNIX was ported to. The Tahoe did help separate out a lot of VAX-specific code from the base, allowing BSD to become more portable, but the Power 6/32 machine quickly disappeared off the market, and not much is known about them.

The CPU was re-sold (under other names) in systems from several vendors (viewed by CCI as OEMs): Unisys sold the 6/32 under the name 'Unisys 7000/40', using their own bastardized BSD+SYSV Unix. (Kuwait Petroleum in Denmark had one of them.) ICL had the 'Clan 7'. Harris had the HCX-5, -7, and -9 models (for which a small amount of information survives - below), running the SysV derivative HCX/UX.

Pixar used a Power 6/32 to render the stained-glass knight in the 1985 movie Young Sherlock Holmes.

Details

The Power 6/32 CPU was implemented in TTL; it had a clock rate of 100nS.

The performance is given in this table, from dhrystone.c (below): 

 *----------------DHRYSTONE VERSION 1.0 RESULTS BEGIN--------------------------
 *
 * MACHINE      MICROPROCESSOR  OPERATING       COMPILER        DHRYSTONES/SEC.
 * TYPE                         SYSTEM                          NO REG  REGS
 * --------------------------   ------------    -----------     ---------------
 * CCI POWER 6/32               COS(SV+4.2)     cc              7500    7800
 * CCI POWER 6/32               POWER 6 UNIX/V  cc              8236    8498
 * CCI POWER 6/32               4.2 Rel. 1.2b   cc              8963    9544
 * VAX 11/780   -               UNIX 5.2        cc              1515    1562
 * VAX 11/780   -               UNIX 4.3bsd     cc              1646    1662

Which may give some indication on the initial reasons why the Power 6/32 was chosen as the successor to the VAX by CSRG.

Instruction Set

Although apparently no documentation survives and is accessible, we can infer a lot from the instruction decoding/printing routines in the debuggers from 4.3 BSD Tahoe, and their input file 'instrs' (below).

  • Instructions start with a 1-byte opcode, and, depending on the opcode and 'addressing mode' (below), are followed by a basic set of 0-3 operands. (Two instructions, 'ediv' and 'emul', take 4 operands; if any operand uses the 'indexed' addressing mode, an extra operand is required for each such use.)
  • Operands start with 1 byte, containing 4 bits of 'addressing mode' and 4 bits of 'register':
    • The CPU has sixteen 32-bit registers r0 ... r13 (fp), r14 (sp), r15 (pc).
    • The addressing modes (reminiscent of those of the PDP-11), and their encodings, are:
Encoding Mode notation
0x0 short literals 0-15  
0x1 short literals 16-31
0x2 short literals 32-47
0x3 short literals 48-63
0x4 indexed [r]
0x5 register immediate r
0x6 register deferred (r)
0x7 auto-decrement -(r)
0x8 auto-increment (r)+
0x9 auto-increment deferred *(r)+
0xA byte displacement BD(r)
0xB byte displacement deferred *BD(r)
0xC short-word displacement WD(r)
0xD short-word displacement deferred *WD(r)
0xE long-word displacement LD(r)
0xF long-word displacement deferred *LD(r)
The "indexed" mode apparently adds the contents of the named register to the address generated by the following operand. (It likely cannot be used with the "register immediate" addressing mode.)
For operands of the 6 'displacement' modes, the operand is followed by a value of the indicated length.

Opcode table

The opcode map and mnemonics for the assembler are as follows:

0 1 2 3 4 5 6 7 8 9 a b c d e f
0x00 halt - - - - sinf ldf ldd addb2 movb addw2 movw addl2 movl bbs -
0x10 nop brb - brw - cosf lnf lnd addb3 cmpb addw3 cmpw addl3 cmpl bbc -
0x20 rei bneq/bnequ - cvtwl - atanf stf std subb2 mcomb subw2 mcomw subl2 mcoml emul aoblss
0x30 bpt beql/beqlu - cvtwb - logf cmpf cmpd subb3 bitb subw3 bitw subl3 bitl ediv aobleq
0x40 ret bgtr - - - sqrtf cmpf2 cmpd2 shll clrb shlq clrw mull2 clrl shal -
0x50 - bleq - - - expf tstf tstd shrl tstb shrq tstw mull3 tstl shar bbssi
0x60 ldpctx - - - - - - pushd - incb - incw divl2 incl - cvtlb
0x70 svpctx jmp - - - - cvlf cvld - decb - decw divl3 decl - cvtlw
0x80 - bgeq movs2 - - - cvfl cvdl orb2 cvtbl orw2 bispsw orl2 adwc adda -
0x90 - blss cmps2 - - - - ldfd orb3 cvtbw orw3 bicpsw orl3 sbwc suba -
0xa0 - bgtru - - - - cvdf - andb2 movzbl andw2 loadr andl2 mtpr ffs -
0xb0 - blequ - - - - negf negd andb3 movzbw andw3 storer andl3 mfpr ffc calls
0xc0 prober bvc movs3 movzwl - - addf addd xorb2 movob xorw2 movow xorl2 movpsl btcs kcall
0xd0 probew bvs cmps3 - - - subf subd xorb3 pushb xorw3 pushw xorl3 pushl - -
0xe0 insque bgequ/bcs - - - - mulf muld mnegb movab mnegw movaw mnegl moval - -
0xf0 remque bcc/blssu - - - - divf divd movblk pushab - pushaw casel pushal callf -

A number of the more complex arithmetic instructions, many of them the floating point and the trigonometric ones (CVLF, CVLD, CVFL, CVDL, LDFD, CVDF, ADDF, ADDD, SUBF, SUBD, MULF, MULD, DIVF, DIVD, SINF, COSF, ATANF, LOGF, SQRTF and EXPF), do not seem to be implemented in the Power 6/32; instead, they were emulated in software, after an attempt to execute them resulted in a trap.

See also

External links

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