PDP-11 architecture

The PDP-11 was an influential and widely-used family of 16-bit minicomputers designed by DEC, in production from 1970-1990. Although the basic address space was 16 bits, most models could hold more main memory than that, although only a limited subset was visible to the program at any time.

The CPU had 8 general purpose registers; the operand coding, which was applied regularly across essentially the entire instruction set, allowed it to provide a two-address instruction architecture, not a simple load-store architecture like its predecessor, the 12-bit PDP-8.

One of the registers (R7) was dedicated to be the Program Counter, and one (R6) was more or less dedicated to be the Stack Pointer. (Other registers can be used as stack pointers, but the hardware uses this one for subroutine call and return, interrupts, traps, etc.) (There are a number of sometimes poorly-documented details of PDP-11 stack operation; see here for more.)

These registers, along with a variety of register-based addressing modes, allowed it to provide a variety of additional operand types, such as immediate (literal) data, absolute and relative addresses, and stack operations; very impressive on a machine which had only 16-bit words (and thus instructions).

The regular application of the operand coding across essentially the entire instruction set allowed these additional operand types to be widely available; this, and the power of the large range of operand modes, substantially reduced the code size. This was an important consideration both in the PDP-11's early life, when small and expensive core memory was the standard main memory; and in its later life, when the 16-bit address space became a severe limit.

Most instructions come in both byte and word data forms; an exception is ADD and SUB, which exist in only word forms (probably because there was not enough room in the instruction set to have them both in both forms).

On CPU models intended for use in time-sharing systems, two CPU modes, Kernel and User, were supported, along with memory management.

Early PDP-11's were all built around the UNIBUS bus; later models switched to the QBUS, which used less pins.

Extensions

The first PDP-11 (the PDP-11/20) was limited to one-bit shift operations, and did not have hardware integer multiplication or division, or any hardware floating point. (An option, the KE11-A Extended Arithmetic Element, did provide multiply, divide, etc in hardware, but it was a separate peripheral on the UNIBUS, not part of the CPU.)

The next model, the PDP-11/45, added both of these classes (the latter as an option), although the follow-on low-cost machines, the PDP-11/05 and PDP-11/04, again did not have either.

Later machines tended to include the former group - although on some early mid-range machines such as the PDP-11/40 and LSI-11s, they were only an option. Floating point was also added to the later machines (although only as an option, until relatively late in the line).

Late in the PDP-11 family's lifetime, a Commercial Instruction Set was defined, and made available as an option in some of the later machines.

Floating point

Two forms of floating point were added: a simplified form, FIS floating point, with only the 4 basic operations, using 32-bit data, in a few early machines; and full-blown floating point (32-bit and 64-bit formats, many operations), FP11 floating point.

The former was available as an option in the PDP-11/40, and later in the PDP-11/03. The latter was available as an option in the PDP-11/45 and variants thereof (the PDP-11/50 and PDP-11/55), the PDP-11/70, PDP-11/34, PDP-11/44 and PDP-11/23; it was standard in the KDJ11 CPUs (although in these machines an optional FPJ11 floating point accelerator greatly improved the floating point performance).

Memory management and CPU modes

After a few disparate custom add-on units to provide memory management and CPU modes in the PDP-11/20, they became standardized with the PDP-11/45 (in which memory management was an option); most later machines supported them. A simplified version was supported in the -11/40 and -11/23 (as an option, in both), and in the -11/34 (standard) and PDP-11/60 (the lack of the full-blown version was a significant handicap in what was a relatively high-end machine).

Operands

The PDP-11 supported both single- and double-operand instructions. The operands are mostly the most flexible form, in which a 6-bit field holds three bits of register number, and three bits of mode. (Which is why PDP-11 object code is usually displayed in octal, as it is the optimal base for that, since each operand field will be in one octal 'digit'.)

As noted above, this operand form provided a large variety of operand types, including stack push and pop, literals, etc. This provides the basic instruction group with great flexibility, especially the double-operand instructions (MOV, ADD, etc).

A few instructions (mostly those which were added to the instruction repertoire later, e.g. MUL, DIV, XOR, etc) only provide a register number for one operand (i.e. if not already in a register, that operand must be pre-loaded into one by another instruction).

Addressing modes

The mode field is further subdivided into a 'Deferred' (indirect) bit, and a two bit field which selects among direct register, auto-increment, auto-decrement, and indexed modes. The indirect bit is the low bit, so odd values of the mode 'digit' are indirect.

The 'regular' modes are:

Mode	Name	Symbolic	Description
0	Register	R	(R) is the operand
2	Auto-increment	(R)+	(R) is the address; (R) is then incremented by 1 or 2, in case of byte or word instructions.
4	Auto-decrement	-(R)	(R) is decremented by 1 or 2, in case of byte or word instructions; R is then the address.
6	Index	X(R)	(R) + X is the address.

(in the last, X is the word after the instruction), and the indirect modes are:

Mode	Name	Symbolic	Description
1	Register deferred	@R or (R)	(R) contains address of operand
3	Auto-increment deferred	@(R)+	(R) is the address of the address; (R) is then incremented by 2
5	Auto-decrement deferred	@-(R)	(R) is decremented by two; (R) is then the address of the address.
7	Index deferred	@X(R)	(R) + X is the address of the address

As mentioned, auto-increment and auto-decrement allow any register to be used as a stack pointer, but the hardware enforces the use of R6 as the SP, so it is un-common for another register to be used for this.

Note that when destination operands use auto-increment or auto-decrement mode, the modification is only made on the first use of the operand; the second uses the same address as that used by the first. (This makes sense; the microcode (or state machine, in the KA11 CPU) calculates the address of the second operand once, and saves that address in a temporary register - usually, but not necessarily, the Bus Address Register. Then, for the write, it just re-uses that value.)

The use of auto-increment mode with the PC as the register used provides literal operands (both immediate, and absolute addresses); indexed modes with the PC can be used for location-independent code.

Instruction set

The instruction set provided a number of double-operand instructions:

• MOV
• ADD
• SUB
• BIT (bit test)
• BIS (bit set)
• BIC (bit clear)

(as noted, ADD and SUB are only available in word mode), and many single-operand instructions:

• CLR
• TST (compare with 0)
• INC
• DEC
• NEG
• COM (complement)
• ASR (arithmetic shift right)
• ASL
• ROR (rotate right)
• ROL
• SWAB (swap bytes)
• ADC (add carry)
• SBC

Condition codes and conditional branches

The instruction set provided a plethora of branches, although all branches are limited to a range of 127 words before or after the current instruction; a limit which is not onerous in practise. All the conditional branches depend on a prior instruction to set 4 condition codes (stored in the Processor Status Word):

• Z - Zero
• N - Negative (i.e. high bit set)
• C - Carry
• V - Overflow

Conditional branches:

• BR (un-conditional)
• BNE (non-zero)
• BEQ (zero)
• BMI (negative)
• BPL (positive)
• BVC (overflow clear)
• BVS (overflow)
• BCS (carry)
• BCC (no carry)

Signed branches:

• BGE (greater than or equal to 0)
• BGT
• BLE
• BLT

Unsigned branches:

• BHIS (higher than, or the same)
• BHI
• BLOS
• BLO

Miscellaneous

Other flow of control instructions (both JMP and JSR) can transfer to any location in the address space):

• JMP
• JSR - subroutine call
• RTS - subroutine return

A variety of other instructions (e.g. to trap to the operating system, halt the CPU, etc) also exist.

Added later

The PDP-11/45 added a few miscellaneous instructions:

• SOB (decrement and conditionally branch)
• XOR (word only, and also only provides a register number for one operand)
• SXT (sign extend, word only)
• MARK (subroutine argument setup)
• RTT (return from interrupt while inhibiting 'trace' trap)
• SPL (set CPU priority level)

All of these, with the exception of SPL, appeared in all later models (except the -11/05 and -11/04).

Various later models added various instructions for Processor Status Word (PS) access, maintenance, etc.

Processor Status Word

All PDP-11's have a Processor Status Word register.The contents vary from model to model, but in all of them it contains: the four condition code bits; a bit to control 'trace' traps (which allow single-stepping the CPU); and the CPU's current priority level (to allow or defer peripheral interrupts). On models which provide memory management, there are two fields to specify the current and previous modes. Some models provide two sets of general CPU registers (only one may be in use at any time); in those machines, a bit in the PSW selects which one is in use.

The layout of the PSW is:

Current Mode		Previous Mode		Register Set	Unused			Priority			T	N	Z	V	C
15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00

Some of the 'unused' bits (above) have uses on particular models; for example, in the -11/44's KD11-Z CPU, bit 8 is used to indicate that a Commercial Instruction Set instruction is in process, but not completed (visible when the PS is saved in an interrupt).

The PSW appears at address 0177776 on most models (0777776 on the UNIBUS, in models with a UNIBUS); the sole exception is the LSI11 CPUs, on which it can only be read/written directly with the MFPS/MTPS instructions (which appear on some, but not all, models).

Depending on the CPU's model (and current mode, for those which support multiple modes), not all bits can be written directly, though. Consult the "PDP-11 Family Differences" appendix, in the PDP-11 Architecture Handbook (1983-84 version) or the MICRO/PDP-11 Handbook (1983-84 version) for details.

Virtualization

The PDP-11 is impossible to virtualize, since there are a number of instructions used by operating systems which do not trap when executed by a program running in User mode. HALT does trap, but not others, including:

• RESET
• WAIT
• RT[IT]
• SPL
• M[TF]P[ID]
• M[TF]PS

Of these, in user mode RESET is a no-op, RT[IT] cannot change the current and previous modes, MFPI acts like MPFD in User mode when the previous mode is also User (to prevent 'theft' of proprietary code), and MTPS can only set the condition codes.

See also

• PDP-11 Memory Management
• PDP-11 Extended Instruction Set
• PDP-11 Commercial Instruction Set
• PDP-11 stacks
• UNIBUS map
• PDP-11 family differences appendix

External links

• PDP-11 instruction reference
• What is the PDP-11 instruction set?
• Digital PDP11 Programming Card
• The PDP-11: A Case Study of How Not to Design Condition Codes