Difference between revisions of "KDJ11-A CPU"

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[[Image:KDJ11-A.jpg|150px|thumb|right|KDJ11-A CPU]]
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[[Image:KDJ11-A.jpg|200px|thumb|right|KDJ11-A CPU]]
  
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The '''KDJ11-A''' CPU board (M8192) is the first [[QBUS]] [[CPU]] card using the [[J-11]] chip of the [[PDP-11]]. It is a [[DEC card form factor|dual-height]] board, and was used to upgrade [[PDP-11/23]] systems. (Confusingly, no DEC 'PDP-11/xx' system is specified as using the KDJ11-A.)
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The '''KDJ11-A CPU''' board (M8192) is the first [[QBUS]] [[PDP-11]] [[Central Processing Unit|CPU]] card using the [[J-11 chip set]]. It is a [[DEC card form factor|dual-height]] board, and was used to upgrade [[PDP-11/23]] systems. (Confusingly, no DEC 'PDP-11/xx' system is specified as using the KDJ11-A.)
  
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It contains an 8K-byte write-through cache (set size 1, block size 1 16-bit word), protected by parity; cache control logic inspects [[DMA]] transfers and invalidates cache entries for memory which is written to by a device.
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It contains an 8K-byte write-through [[cache]] (set size 1, block size 1 16-bit word), protected by [[parity]]; cache control logic inspects [[Direct Memory Access|DMA]] transfers on the QBUS and invalidates cache entries for [[main memory]] which is written to by a [[peripheral|device]].
  
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It also provides a set of diagnostic [[LED]]s, and a Line Time Clock; but no other devices (boot PROM, serial line, etc).
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It also provides a set of diagnostic [[Light Emitting Diode|LED]]s, and a [[line time clock]]; but no other devices (boot [[PROM]], [[serial line]], etc). Both the LTC, and its control [[register]], are enabled by a single configuration [[jumper]] (below).
  
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Although the J-11 does implement FP11 floating-point, the board can use the FPJ11 Floating Point Accelerator (note that only the -YB version of the board operates correctly with the FPJ11).
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Although the J-11 does implement [[FP11 floating point|FP11]] floating-point, the board can also use the optional [[FPJ11 floating point accelerator]] [[integrated circuit|chip]]; note that only the -YB version of the board operates correctly with the FPJ11.
  
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{{PDP-11}}
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==Configuration==
  
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[[Category:QBUS processors]]
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A limited amount of configuration can be done with a set of nine jumpers (in the middle of the card).Their functions are:
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{| class="wikitable" | border=1
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! Jumper !! Function !! In || Out
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|-
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|W1 || [[Bootstrap]] [[address]] bit 15 || 1 || 0
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|-
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|W2 || Bootstrap address bit 14 || 1 || 0
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|-
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|W3 || Powerup option bit 2
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|-
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|W4 || Bootstrap address bit 13 || 1 || 0
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|-
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|W5 || [[Halt]] enable || Halt || [[Trap]] to 4
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|-
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|W6 || Bootstrap address bit 12 || 1 || 0
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|-
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|W7 || Powerup option bit 1
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|-
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|W8 || Wakeup circuit || Disabled || Enabled
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|-
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|W9 || BEVNT/LTC register || Disabled || Enabled
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|}
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Powerup options are:
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{| class="wikitable" | border=1
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! W3 !! W7 !! Action
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|-
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| In || In || [[Program Counter|PC]] from 024, [[Processor Status Word|PS]] from 026
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|-
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| In || Out || [[QBUS CPU ODT|ODT]], PS=0
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|-
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| Out || In || PC=0173000, PS=340
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|-
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| Out || Out || PC=configuration jumpers, PS=340
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|}
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==Further reading==
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* ''Compatible Bootstrap for the LSI-11/73'', [[MicroNote]] #114
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* ''LSI-11/73 Upgrade Paths'', [[MicroNote]] #115
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==External links==
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* [http://www.bitsavers.org/pdf/dec/pdp11/1173/EK-KDJ1A-UG-002_KDJ11-A_CPU_Module_Users_Guide_2ed_Jun86.pdf KDJ11-A CPU Module User's Guide] (EK-KDJ1A-UG-002)
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* [http://www.bitsavers.org/pdf/dec/pdp11/1173/MP01890_KDJ11-A_Jan84.pdf KDJ11-A Field Maintenance Print Set] (MP01890-01)
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[[Category: PDP-11 QBUS Processors]]

Latest revision as of 20:02, 1 August 2024

KDJ11-A CPU

The KDJ11-A CPU board (M8192) is the first QBUS PDP-11 CPU card using the J-11 chip set. It is a dual-height board, and was used to upgrade PDP-11/23 systems. (Confusingly, no DEC 'PDP-11/xx' system is specified as using the KDJ11-A.)

It contains an 8K-byte write-through cache (set size 1, block size 1 16-bit word), protected by parity; cache control logic inspects DMA transfers on the QBUS and invalidates cache entries for main memory which is written to by a device.

It also provides a set of diagnostic LEDs, and a line time clock; but no other devices (boot PROM, serial line, etc). Both the LTC, and its control register, are enabled by a single configuration jumper (below).

Although the J-11 does implement FP11 floating-point, the board can also use the optional FPJ11 floating point accelerator chip; note that only the -YB version of the board operates correctly with the FPJ11.

Configuration

A limited amount of configuration can be done with a set of nine jumpers (in the middle of the card).Their functions are:

Jumper Function In Out
W1 Bootstrap address bit 15 1 0
W2 Bootstrap address bit 14 1 0
W3 Powerup option bit 2
W4 Bootstrap address bit 13 1 0
W5 Halt enable Halt Trap to 4
W6 Bootstrap address bit 12 1 0
W7 Powerup option bit 1
W8 Wakeup circuit Disabled Enabled
W9 BEVNT/LTC register Disabled Enabled

Powerup options are:

W3 W7 Action
In In PC from 024, PS from 026
In Out ODT, PS=0
Out In PC=0173000, PS=340
Out Out PC=configuration jumpers, PS=340

Further reading

  • Compatible Bootstrap for the LSI-11/73, MicroNote #114
  • LSI-11/73 Upgrade Paths, MicroNote #115

External links

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