Difference between revisions of "RH70 MASSBUS controller"
(Reasonably complete) |
m (→External links: +RH70 Self-Paced Course) |
||
| (4 intermediate revisions by the same user not shown) | |||
| Line 1: | Line 1: | ||
The '''RH70 MASSBUS controller''' allowed the interconnection of [[MASSBUS]] devices such as the [[RP04 disk drive|RP04]] to a [[PDP-11/70]]. | The '''RH70 MASSBUS controller''' allowed the interconnection of [[MASSBUS]] devices such as the [[RP04 disk drive|RP04]] to a [[PDP-11/70]]. | ||
| − | One the -11/70 side, it contains connections to both the -11/70's [[main memory]] [[cache]] (for data reads and writes from the device), as well as to the [[UNIBUS]] (for [[interrupt]]s, and access to the device's [[register]]s by the [[Central Processing Unit|CPU]]). | + | One the -11/70 side, it contains connections to both the -11/70's [[main memory]] and [[cache]] (for data reads and writes from the device), as well as to the [[UNIBUS]] (for [[interrupt]]s, and access to the device's [[register]]s by the [[Central Processing Unit|CPU]]). |
| − | The connection to the cache is purely for data transfer control purposes; all data reads and writes go directly to the actual main memory. A write to a main memory location which is stored in the cache invalidates that cache entry. | + | The connection to the cache is purely for data transfer control purposes; all data reads and writes go directly to the actual main memory (although the RH70's access to the main memory bus is controlled by the cache). A write to a main memory location which is stored in the cache invalidates that cache entry. |
==Hardware== | ==Hardware== | ||
| Line 19: | Line 19: | ||
* M8152 - BCT - bus control | * M8152 - BCT - bus control | ||
| − | Three | + | Three dual-height M5904 MASSBUS transceiver modules. |
==Registers== | ==Registers== | ||
| Line 34: | Line 34: | ||
As is standard for the MASSBUS, all the other device registers are in the device. | As is standard for the MASSBUS, all the other device registers are in the device. | ||
| + | |||
| + | ==External links== | ||
| + | |||
| + | * [http://www.bitsavers.org/pdf/dec/unibus/CSS-MO-F-5.2-27_RH70_Option_Description_Feb77.pdf RH70/Special Massbus Controller Option Description] (CSS-MO-F-5.2-27) | ||
| + | * [http://www.bitsavers.org/pdf/dec/unibus/RH70_Engineering_Drawings_Apr75.pdf RH70 Engineering Drawings] | ||
| + | * [https://manx-docs.org/collections/antonio/arc-db/EY-D3024-WB-001.pdf RH11/RH70 MASSBUS Controllers Self-Paced Course] | ||
| + | |||
| + | [[Category: MASSBUS Controllers]] | ||
Latest revision as of 14:45, 25 February 2022
The RH70 MASSBUS controller allowed the interconnection of MASSBUS devices such as the RP04 to a PDP-11/70.
One the -11/70 side, it contains connections to both the -11/70's main memory and cache (for data reads and writes from the device), as well as to the UNIBUS (for interrupts, and access to the device's registers by the CPU).
The connection to the cache is purely for data transfer control purposes; all data reads and writes go directly to the actual main memory (although the RH70's access to the main memory bus is controlled by the cache). A write to a main memory location which is stored in the cache invalidates that cache entry.
Hardware
Each RH70 (up to a maximum of 4) consisted of a special pre-wired 4-slot section of the CPU's backplane, into which plugged a number of cards:
One hex-sized:
- M8150 - MDP - Data buffer and parity
Three quad-sized:
- M8151 - CST - Control and Status
- M8152 - AWR - Address and Word Count registers
- M8152 - BCT - bus control
Three dual-height M5904 MASSBUS transceiver modules.
Registers
The RH70 contains 6 registers, plus a share of a seventh; they are
- RHCS1 - Control and Status 1 (shared)
- RHWC - Word Count
- RHBA - Bus Address
- RHBAE - Bus Address Extension
- RHCS2 - Control and Status 2
- RHCS3 - Control and Status 3
- RHDB - Data Buffer (for maintenance)
As is standard for the MASSBUS, all the other device registers are in the device.
