Difference between revisions of "DL10 PDP-11 Data Link"

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(Add note about how the secnd octet selects the mode)
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The '''DL10 PDP-10/PDP-11 Interface Channel''' connects [[PDP-10]] [[mainframe]]s to [[PDP-11]]s used as communication [[front end]]s; up to 4 PDP-11's per DL10. It allows the PDP-10 to 'see' into the PDP-11's [[main memory]], and vice versa (although the ability of the PDP-11 to do so is limited by the DL10's settings).
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The '''DL10 PDP-11 Data Link''' connects [[PDP-10]] [[mainframe]]s to [[PDP-11]]s used as communication [[front end]]s; up to 4 PDP-11's per DL10. It allows the PDP-10 to 'see' into the PDP-11's [[main memory]], and vice versa (although the ability of the PDP-11 to do so is limited by the DL10's settings).
  
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On the PDP-10 side, it connected to the PDP-10 memory bus, and also to two I/O busses (allowing it to be controlled by both processors in a multi-[[Central Processing Unit|CPU]] system. So, it could be connected to [[KA10]]s and [[KI10]]s, but only to [[KL10]]s with the optional old-style I/O busses.
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On the PDP-10 side, it connected to the [[PDP-10 Memory Bus]], and also up to two [[PDP-10 I/O Bus]]ses (allowing it to be controlled by both processors in a multi-[[Central Processing Unit|CPU]] system). So, it could be connected to [[KA10]]s and [[KI10]]s, but only to [[KL10]]s with the optional old-style Memory and I/O [[bus]]ses (provided by the [[DMA20 Memory Bus Adapter]] and [[DIA20 IBus Adapter‎]] respectively).
  
 
On the PDP-11 side, PDP-11's connected to the DL10 have a special console which has a cable which goes to the DL10, which allows the PDP-10 to start and stop the PDP-11; the PDP-11's [[UNIBUS]] runs into the DL10 and is plugged into the DL10's backplane.
 
On the PDP-11 side, PDP-11's connected to the DL10 have a special console which has a cable which goes to the DL10, which allows the PDP-10 to start and stop the PDP-11; the PDP-11's [[UNIBUS]] runs into the DL10 and is plugged into the DL10's backplane.
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The DL10 is used in the [[DN87 Universal Synchronous/Asynchronous Communications Front End Subsystem]].
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There is little remaining DL10 documentation, alas; see below for links to what exists online.
  
 
==Data formats==
 
==Data formats==
  
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Note that the format is selected by the second octed in the word; the values used in that octet to select the byte size in the 'pointer' mode are disjoint from the values used in that octet for the other modes.
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Note that the format is selected by the second octet in the word; the values used in that octet to select the byte size in the 'pointer' mode are disjoint from the values used in that octet for the other modes.
  
 
===Immediate mode===
 
===Immediate mode===
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| 11 interrupt || || 10 interrupt || || Nonex memory || ||  Set parity error ||  || Word count overflow || || This port enabled || || Error interrupt enable || 11 interrupt enable || colspan=2 | Interrupt assignment
 
| 11 interrupt || || 10 interrupt || || Nonex memory || ||  Set parity error ||  || Word count overflow || || This port enabled || || Error interrupt enable || 11 interrupt enable || colspan=2 | Interrupt assignment
 
{{16bit-bitout}}
 
{{16bit-bitout}}
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==PDP-10 standard instructions==
 
==PDP-10 standard instructions==
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CONO DLC,
 
CONO DLC,
 
{{36bithalf-header}}
 
{{36bithalf-header}}
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| Clear DL10 || Lock DL10 || 11 interrupt || Port enable || 10 interrupt || 11 interrupt || Port enable || 10 interrupt || 11 interrupt || Port enable || 10 interrupt || 11 interrupt || Port enable || 10 interrupt || colspan=3 | Priority interrupt assignment
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| Clear DL10 || Lock DL10 || Action of 1s ||| 11 interrupt || Port enable || 10 interrupt || 11 interrupt || Port enable || 10 interrupt || 11 interrupt || Port enable || 10 interrupt || 11 interrupt || Port enable || 10 interrupt || colspan=3 | Priority interrupt assignment
 
{{36bithalf-bitout}}
 
{{36bithalf-bitout}}
  
 
CONI DLB,
 
CONI DLB,
 
{{36bit-header}}
 
{{36bit-header}}
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| Diag || Diag msyn || Diag C0 || Diag C1 || Diag R2 || Diag R1 || Diag INH CYC || || 11-3 8K option || 11-2 8K option || 11-1 8K option || 11-0 8K option || IOC lock on || ~IOC lock delay on || ~IOC lock 1 out || ~IOC lock 0 out || 18-bit address || || Got DL10 locked || || 11 interrupt || Port enable || 10 interrupt || 11 interrupt || Port enable || 10 interrupt || 11 interrupt || Port enable || 10 interrupt || 11 interrupt || Port enable || 10 interrupt || colspan=3 | Priority interrupt assignment
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| Diag || Diag msyn || Diag C0 || Diag C1 || Diag R2 || Diag R1 || Diag INH CYC || || 11-3 8K option || 11-2 8K option || 11-1 8K option || 11-0 8K option || IOC lock on || ~IOC lock delay on || ~IOC lock 1 out || ~IOC lock 0 out || 18-bit address || Standard interrupt || || Got DL10 locked || || 11 interrupt || Port enable || 10 interrupt || 11 interrupt || Port enable || 10 interrupt || 11 interrupt || Port enable || 10 interrupt || 11 interrupt || Port enable || 10 interrupt || colspan=3 | Priority interrupt assignment
 
{{36bit-bitout}}
 
{{36bit-bitout}}
  
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[[Category:Peripherals]]
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==External links==
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* [http://pdp-10.trailing-edge.com/bb-d549g-sb/01/boot11.mem.html BOOT11 - PDP-11 Bootstrap From PDP-10] - contains general description of the DL10 in section 4.0
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* [http://www.bitsavers.org/pdf/dec/pdp10/KL10/EK-108OU-PD-002_KL10-Based_Physical_Description_Mar77.pdf KL10-Based Physical Description] - the DL10 is covered in Sections 1.8
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* [http://bitsavers.org/www.computer.museum.uq.edu.au/pdf/DEC-10-XSRMA-A-D%20DECsystem10%20System%20Reference%20Manual.pdf DECsystem-10 System Reference Manual] - documents the PDP-10's DL10 control instructions in Appendix C (on pp. 365-368 of the PDF)
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* [http://www.bitsavers.org/pdf/dec/pdp10/periph/MP00068_DN87_Universal_Comm_System_Front_End_Jan76.pdf DN87 Field Maintenance Print Set] - contains complete engineering drawings for the DL10 (on pp. 100-212 of the PDF)
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[[Category: PDP-10 Machine Interfaces]]
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[[Category: UNIBUS Machine Interfaces]]

Latest revision as of 16:27, 7 November 2023

The DL10 PDP-11 Data Link connects PDP-10 mainframes to PDP-11s used as communication front ends; up to 4 PDP-11's per DL10. It allows the PDP-10 to 'see' into the PDP-11's main memory, and vice versa (although the ability of the PDP-11 to do so is limited by the DL10's settings).

On the PDP-10 side, it connected to the PDP-10 Memory Bus, and also up to two PDP-10 I/O Busses (allowing it to be controlled by both processors in a multi-CPU system). So, it could be connected to KA10s and KI10s, but only to KL10s with the optional old-style Memory and I/O busses (provided by the DMA20 Memory Bus Adapter and DIA20 IBus Adapter‎ respectively).

On the PDP-11 side, PDP-11's connected to the DL10 have a special console which has a cable which goes to the DL10, which allows the PDP-10 to start and stop the PDP-11; the PDP-11's UNIBUS runs into the DL10 and is plugged into the DL10's backplane.

The DL10 is used in the DN87 Universal Synchronous/Asynchronous Communications Front End Subsystem.

There is little remaining DL10 documentation, alas; see below for links to what exists online.

Data formats

Note that the format is selected by the second octet in the word; the values used in that octet to select the byte size in the 'pointer' mode are disjoint from the values used in that octet for the other modes.

Immediate mode

Unused 0 or 7 Unused Data
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

Indirect mode

A P 1 Unused Address
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
A Access
0 Read or write
1 Read only
P 16-bit word position within 36-bit word
0 Bits 0-15
1 Bits 16-31
2 Bits 20-35
3 Bits 2-17

Pointer modes

P S Word count Address
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

Bytes are left-justified inside a 36-bit word.

S Byte size
2 16
3 12
4 8
5 7
6 6

PDP-11 control and status registers

DATO 100000 (Conditions out)

Set 11 interrupt Clear 11 interrupt Set 10 interrupt Clear 10 interrupt Set nonex memory Clear nonex memory Set parity error Clear parity error Set word count overflow Clear word count overflow Error interrupt enable 11 interrupt enable Interrupt assignment
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

DATI 100000 (Status)

11 interrupt 10 interrupt Nonex memory Set parity error Word count overflow This port enabled Error interrupt enable 11 interrupt enable Interrupt assignment
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

PDP-10 standard instructions

CONO DLB,

Base address Mask for size of pointer block PDP-11
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

CONO DLC,

Clear DL10 Lock DL10 Action of 1s 11 interrupt Port enable 10 interrupt 11 interrupt Port enable 10 interrupt 11 interrupt Port enable 10 interrupt 11 interrupt Port enable 10 interrupt Priority interrupt assignment
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

CONI DLB,

Diag Diag msyn Diag C0 Diag C1 Diag R2 Diag R1 Diag INH CYC 11-3 8K option 11-2 8K option 11-1 8K option 11-0 8K option IOC lock on ~IOC lock delay on ~IOC lock 1 out ~IOC lock 0 out 18-bit address Standard interrupt Got DL10 locked 11 interrupt Port enable 10 interrupt 11 interrupt Port enable 10 interrupt 11 interrupt Port enable 10 interrupt 11 interrupt Port enable 10 interrupt Priority interrupt assignment
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

External links

Retrieved from "https://gunkies.org/w/index.php?title=DL10_PDP-11_Data_Link&oldid=31842"