Difference between revisions of "KUV11 Writeable Control Store"

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The principle hardware debugging aid is the 'micro-[[address]] trace [[Random Access Memory|RAM]]', which is a 16-entry record of consecutive micro-addresses emitted as the micro-program runs, which can be frozen under program control, using one of the two extra bits in the extended micro-word.
 
The principle hardware debugging aid is the 'micro-[[address]] trace [[Random Access Memory|RAM]]', which is a 16-entry record of consecutive micro-addresses emitted as the micro-program runs, which can be frozen under program control, using one of the two extra bits in the extended micro-word.
  
==Further reading==
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==External links==
  
* ''LSI-11 WCS User's Guide'', EK-KUV11-TM-001
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* [http://www.bitsavers.org/pdf/dec/pdp11/1103/ PDP-11/03] - documentation at [[Bitsavers]]
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** [http://www.bitsavers.org/pdf/dec/pdp11/1103/EK-KUV11-TM_LSI11_WCS.pdf LSI-11 WCS user's guide] (EK-KUV11-TM-001)
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** [http://www.bitsavers.org/pdf/dec/pdp11/1103/LSI-11_User_Microcoding_Preliminary.pdf LSI-11 User Microcoding Preliminary]
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** [http://www.bitsavers.org/pdf/dec/pdp11/1103/M8018_LSI-11_WCS_Schematic.pdf Writeable Control Store Engineering Drawings]
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* [http://www.vaxarchive.org/hardware/pdp11/wcsrc.tar WCS reference card] (images in TAR file)
  
{{PDP-11}}
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[[Category: PDP-11 QBUS Processors]]
 
 
[[Category: PDP-11 Processors]]
 

Latest revision as of 20:12, 2 July 2023

The KUV11 Writeable Control Store is an option for the LSI-11 which provides a user-programmable microcode memory extension, along with some hardware aids to debugging micro-programs. It allows additional, custom instructions to be added to the PDP-11 instruction set.

It consists of a quad card (M8018) which plugs into the QBUS backplane close to the CPU card, and a flat cable which runs from the KUV11 to a free micro-ROM chip socket on the CPU card, and gives the KUV11 access to the micro-instruction bus.

The micro-store consists of 24 1Kx1 high-speed static RAM chips. The LSI-11 micro-word is 22 bits long; the extra two bits are fed to backplane pins (AE1 and AF1) to provide high-speed controls. A DIP switch on the KUV11 controls where the micro-store appears in the micro-address space.

The micro-words themseves are fed to the LSI-11 over the cable; the LSI-11 does not have the ability to write the micro-store contents over that cable, but has read-write access to it via the QBUS. That bus also provides access to a number of control registers on the KUV11.

The principle hardware debugging aid is the 'micro-address trace RAM', which is a 16-entry record of consecutive micro-addresses emitted as the micro-program runs, which can be frozen under program control, using one of the two extra bits in the extended micro-word.

External links