Difference between revisions of "KB11-A CPU"
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==Parity== | ==Parity== | ||
| − | + | In the ''pdp-11/45 processor handbook'' (1972 and 1973 editions) a little-known "Appendix E: Memory Parity", referred to in "2.5.6 Memory Parity", indicates that there are "16 memory status registers ... each one associated with an 8K section of memory". One bit in each register is 'Halt Enable': "[when] set, the machine will execute a [[halt]] if a parity error occurs". (When clear, the machine will [[trap]] to 4!) | |
| − | + | These registers, despite the impression given here, are not actually in the KB11-A, but rather in the MS11. | |
| − | + | A very early version of the KB11-A, which actually made it into the field, does halt the CPU on a parity error on the UNIBUS. This was later changed to the canonical trap to 0114. | |
| − | * [http:// | + | ==External links== |
| + | |||
| + | * [http://www.bitsavers.org/pdf/dec/pdp11/1145/KB11-A_Maint.pdf KB11-A central processor unit maintenance manual] (DEC-11-HKBB-D) | ||
| + | * [http://www.bitsavers.org/pdf/dec/pdp11/1145/EK-KB11A-MM-004_Aug76.pdf KB11-A,D central processor unit maintenance manual] (EK-KB11A-MM-004) | ||
| + | * [http://www.bitsavers.org/pdf/dec/pdp11/1145/KB11-A_revS_Engineering_Drawings_Dec1973.pdf KB11-A central processor unit engineering drawings] (KB11A-19-S) | ||
| + | * [http://www.bitsavers.org/pdf/dec/pdp11/1145/KB11-A_Central_Processor_Unit_Engineering_Drawings_Apr76.pdf KB11-A central processor unit engineering drawings] (KB11A-65-AA) | ||
==See also== | ==See also== | ||
| Line 43: | Line 48: | ||
* [[KB11-D CPU]] | * [[KB11-D CPU]] | ||
| − | + | [[Category: PDP-11 UNIBUS Processors]] | |
| − | |||
| − | [[Category:PDP-11 | ||
| − | |||
Latest revision as of 20:08, 2 July 2023
The KB11-A CPU is the earlier CPU for the PDP-11/45. The optional FP11-B Floating-Point Processor and KT11-C Memory Management Unit of the PDP-11/45 plugged into the CPU's backplane.
In addition to main memory on the UNIBUS, the KB11-A could also use the special high-speed MS11 Semiconductor Memory System, specific to the PDP-11/45, which plugged into a special bus, the Fastbus, which was also part of the CPU's backplane.
The KB11-A was the first of a series of PDP-11 CPUs which were modified versions of this design.
Contents
Boards
The KB11-A board set included:
- M8100 Data and Address Paths
- M8101 General Register and Control
- M8102 Instruction Register and Decode
- M8103 ROM and ROM Control
- M8104 Processor Data and UNIBUS Registers
- M8105 Timing and Miscellaneous Control
- M8106 UNIBUS and Console Control
- M8109 Timing Generator
In addition, the CPU includes either:
- M8116 Segmentation Jumper Board
used when the KT11-C Memory Management Unit is not present, or:
- M8107 Segmentation Address Paths
- M8108 Segmentation Status Registers
which comprise the KT11-C.
Parity
In the pdp-11/45 processor handbook (1972 and 1973 editions) a little-known "Appendix E: Memory Parity", referred to in "2.5.6 Memory Parity", indicates that there are "16 memory status registers ... each one associated with an 8K section of memory". One bit in each register is 'Halt Enable': "[when] set, the machine will execute a halt if a parity error occurs". (When clear, the machine will trap to 4!)
These registers, despite the impression given here, are not actually in the KB11-A, but rather in the MS11.
A very early version of the KB11-A, which actually made it into the field, does halt the CPU on a parity error on the UNIBUS. This was later changed to the canonical trap to 0114.
External links
- KB11-A central processor unit maintenance manual (DEC-11-HKBB-D)
- KB11-A,D central processor unit maintenance manual (EK-KB11A-MM-004)
- KB11-A central processor unit engineering drawings (KB11A-19-S)
- KB11-A central processor unit engineering drawings (KB11A-65-AA)
