Difference between revisions of "Systems Concepts DC-10"
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| − | The [[Systems Concepts]] | + | The '''DC-10''' from [[Systems Concepts]] is a [[PDP-10]] [[disk]] [[device controller|controller]] which interfaced with [[International Business Machines|IBM]] 2311/2314 compatible drives. It connected to both the [[PDP-10 I/O Bus]] and to the [[PDP-10 Memory Bus]]; it did not need a separate [[channel]] (e.g. a [[DF10 Data Channel|DF10]]). |
| + | |||
| + | The actual drives used at MIT were [http://chmhdd.wikifoundry.com/page/Memorex+660 Memorex Model 660], compatible with the 2314, and later [[Calcomp Model 215]]'s, also compatible with the 2314, but offering double density. | ||
| + | |||
| + | The PDP-10 I/O device covers two device codes: 610 and 614, which are conventionally named DC0 and DC1. | ||
| + | |||
| + | The DC-10 shared hardware with the [[Systems Concepts DK-10]], using the same memory bus interface. | ||
| + | |||
| + | === CONI DC0, bits === | ||
| + | |||
| + | {{36bit-header}} | ||
| + | | colspan=18 | Unused || PIRQC || SRQ || colspan=3 | Unused || DEEB || ERR || AEB || ATT || IENB || RUN || ACT || CEB || CHF || CFL || colspan=3 | PIA | ||
| + | {{36bit-bitout}} | ||
| + | |||
| + | === CONO DC0, bits === | ||
| + | |||
| + | {{36bit-header}} | ||
| + | | colspan=18 | Unused || 1 || X || colspan=2 | Unused || DENB || ERR || ATEB || CATT || SRQ || IENB || STAR || SGL || CENB || CFLG || CPUF || colspan=3 | PIA | ||
| + | {{36bit-bitout}} | ||
| + | |||
| + | Set status bits according to mask in 22-32. | ||
| + | |||
| + | {{36bit-header}} | ||
| + | | colspan=18 | Unused || 0 || 1 || colspan=2 | Unused || DENB || ERR || ATEB || CATT || SRQ || IENB || STAR || SGL || CENB || CFLG || CPUF || colspan=3 | PIA | ||
| + | {{36bit-bitout}} | ||
| + | |||
| + | Clear status bits according to mask in 22-32. | ||
| + | |||
| + | === DATAO DC0, === | ||
| + | |||
| + | Writes a channel instruction to be executed immediately. | ||
| + | |||
| + | === CONO DC1, bits === | ||
| + | |||
| + | {{36bit-header}} | ||
| + | | colspan=33 | Unused || colspan=3 | TMDN | ||
| + | {{36bit-bitout}} | ||
| + | |||
| + | === CONI DC1, bits === | ||
| + | |||
| + | {{36bit-header}} | ||
| + | | colspan=2 | Unused || colspan=4 | ATDN || colspan=4 | TMDN || colspan=8 | LAT || colspan=6 | Unused || DIPE || RLNER || RCER || OVRRN || CKSER || WTHER || FUNSF || OFFL || PROT || DOBSY || NXM || CPERR | ||
| + | {{36bit-bitout}} | ||
| + | |||
| + | [[Category: PDP-10 Storage Controllers]] | ||
Latest revision as of 02:13, 24 October 2022
The DC-10 from Systems Concepts is a PDP-10 disk controller which interfaced with IBM 2311/2314 compatible drives. It connected to both the PDP-10 I/O Bus and to the PDP-10 Memory Bus; it did not need a separate channel (e.g. a DF10).
The actual drives used at MIT were Memorex Model 660, compatible with the 2314, and later Calcomp Model 215's, also compatible with the 2314, but offering double density.
The PDP-10 I/O device covers two device codes: 610 and 614, which are conventionally named DC0 and DC1.
The DC-10 shared hardware with the Systems Concepts DK-10, using the same memory bus interface.
CONI DC0, bits
| Unused | PIRQC | SRQ | Unused | DEEB | ERR | AEB | ATT | IENB | RUN | ACT | CEB | CHF | CFL | PIA | |||||||||||||||||||||
| 00 | 01 | 02 | 03 | 04 | 05 | 06 | 07 | 08 | 09 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 |
CONO DC0, bits
| Unused | 1 | X | Unused | DENB | ERR | ATEB | CATT | SRQ | IENB | STAR | SGL | CENB | CFLG | CPUF | PIA | ||||||||||||||||||||
| 00 | 01 | 02 | 03 | 04 | 05 | 06 | 07 | 08 | 09 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 |
Set status bits according to mask in 22-32.
| Unused | 0 | 1 | Unused | DENB | ERR | ATEB | CATT | SRQ | IENB | STAR | SGL | CENB | CFLG | CPUF | PIA | ||||||||||||||||||||
| 00 | 01 | 02 | 03 | 04 | 05 | 06 | 07 | 08 | 09 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 |
Clear status bits according to mask in 22-32.
DATAO DC0,
Writes a channel instruction to be executed immediately.
CONO DC1, bits
| Unused | TMDN | ||||||||||||||||||||||||||||||||||
| 00 | 01 | 02 | 03 | 04 | 05 | 06 | 07 | 08 | 09 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 |
CONI DC1, bits
| Unused | ATDN | TMDN | LAT | Unused | DIPE | RLNER | RCER | OVRRN | CKSER | WTHER | FUNSF | OFFL | PROT | DOBSY | NXM | CPERR | |||||||||||||||||||
| 00 | 01 | 02 | 03 | 04 | 05 | 06 | 07 | 08 | 09 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 |
