Difference between revisions of "DRV11-B Direct Memory Access Interface"

From Computer History Wiki
Jump to: navigation, search
(Basics)
 
m (proper sub-cat)
 
(3 intermediate revisions by the same user not shown)
Line 1: Line 1:
−
The '''DRV11-B Direct Memory Access Interface''' is a parallel port [[device controller]] for the [[QBUS]] which provided a pair of 16-[[bit]] parallel ports, one input, and one output; it uses [[Direct Memory Access|DMA]] to transfer data.
+
The '''DRV11-B Direct Memory Access Interface''' is a [[parallel interface]] [[device controller]] for the [[QBUS]] which provided a pair of 16-[[bit]] parallel ports, one input, and one output; it uses [[Direct Memory Access|DMA]] to transfer data.
  
−
It is effectively a [[half duplex]] device; it has only a single pair of [[bus]] [[address]] and word count [[register]]s. Directional control is by the [[user]]'s device specifying whether each cycle is a DATI, DATO, or DATIO.
+
It is effectively a [[half-duplex]] device; it has only a single pair of [[bus]] [[address]] and word count [[register]]s. Directional control is by the [[user]]'s device specifying whether each cycle is a DATI, DATO, or DATIO.
  
 
It was a [[DEC card form factor|quad]] format card (M7950); connection to the user's device is via a pair of 40-[[pin]] [[Berg connector]]s.
 
It was a [[DEC card form factor|quad]] format card (M7950); connection to the user's device is via a pair of 40-[[pin]] [[Berg connector]]s.
Line 12: Line 12:
 
! Register !! Abbreviation !! Address
 
! Register !! Abbreviation !! Address
 
|-
 
|-
−
|Bus Address Register || DRBAR || 767770
+
|Word Count Register || DRWCR || 767770
 
|-
 
|-
−
|Word Count Register || DRWCR || 767772
+
|Bus Address Register || DRBAR || 767772
 
|-
 
|-
 
|Control and Status Register || DRCSR || 767774
 
|Control and Status Register || DRCSR || 767774
Line 23: Line 23:
 
|}
 
|}
  
−
<!-- In the register contents (below), bits which are read/write or unused are shown in normal font, those which are read-only are in ''italics''.
+
In the register contents (below), bits which are read/write are shown in normal font, those which are read-only are in ''italics'', and write-only in '''bold'''.
 +
 
 +
===Word Count Register (DRWCR)===
 +
{{16bit-header}}
 +
| colspan=16 | WC15 <-> WC0
 +
{{16bit-bitout}}
 +
 
 +
===Bus Address Register (DRBAR)===
 +
{{16bit-header}}
 +
| colspan=15 | BA15 <-> BA1 || 0
 +
{{16bit-bitout}}
  
 
===Status Register (DRCSR)===
 
===Status Register (DRCSR)===
 
{{16bit-header}}
 
{{16bit-header}}
−
| ''REQ B'' || colspan=7 | Unused || ''REQ A'' || INT ENB A || INT ENB B || colspan=3 | Unused || CSR1 || CSR0
+
| ''ERR'' || ''NEX'' || ''ATTN'' || MAINT || colspan=3 | ''STATUS'' || CYCLE || ''RDY'' || IE || colspan=2 | XAD || colspan=3 | FNCT || '''GO'''
 
{{16bit-bitout}}
 
{{16bit-bitout}}
  
−
* REQ B - Request B - Signal from user's hardware which can be tested, or cause an [[interrupt]] (below)  
+
* ERR - Error; set by NEX or ATTN
−
* REQ A - Request A
+
* NEX - Nonexistent Memory; also write-to-zero
−
* INT ENB A - Interrupt Enable A - When set, allows setting REQ A to cause an interrupt  
+
* ATTN - Attention; signal from user's hardware which can be tested, or cause an [[interrupt]] (below)  
−
* INT ENB B - Interrupt Enable B
+
* MAINT - Maintenance
−
* CSR1 - Signal to user's hardware (on connector 1)
+
* STATUS - Signals from user hardware
−
* CSR0 - Signal to user's hardware (on connector 2)
+
* CYCLE - DMA cycle requested
 +
* RDY - DRV11-B is able to accept a new command; set by ERR or WCR overflow, cleared by GO
 +
* IE - Interrupt Enable - When set, allows setting RDY to cause an interrupt  
 +
* XAD - Extended Address; extension of BAR
 +
* FNCT - Signals to user's hardware
 +
* GO - Enables DMA, sent to user's hardware
  
 
===Output Buffer Register (DROUTBUF)===
 
===Output Buffer Register (DROUTBUF)===
Line 45: Line 60:
 
{{16bit-header}}
 
{{16bit-header}}
 
| colspan=16 | ''IN15 <-> IN0''
 
| colspan=16 | ''IN15 <-> IN0''
−
{{16bit-bitout}} -->
+
{{16bit-bitout}}
  
−
[[Category:QBUS Peripherals]]
+
[[Category: QBUS Parallel Interfaces]]

Latest revision as of 02:54, 10 June 2020

The DRV11-B Direct Memory Access Interface is a parallel interface device controller for the QBUS which provided a pair of 16-bit parallel ports, one input, and one output; it uses DMA to transfer data.

It is effectively a half-duplex device; it has only a single pair of bus address and word count registers. Directional control is by the user's device specifying whether each cycle is a DATI, DATO, or DATIO.

It was a quad format card (M7950); connection to the user's device is via a pair of 40-pin Berg connectors.

Registers

The device has five control and buffer registers, which can be configured to any group of four sequential word locations in the I/O page; the first DRV11-B is normally configured to addresses 772410-72416. The two buffer registers share an address, responding to read or write cycles as the case might be.

Register Abbreviation Address
Word Count Register DRWCR 767770
Bus Address Register DRBAR 767772
Control and Status Register DRCSR 767774
Input Data Buffer Register DRINBUF 767776 (read)
Output Data Buffer Register DROUTBUF 767776 (write)

In the register contents (below), bits which are read/write are shown in normal font, those which are read-only are in italics, and write-only in bold.

Word Count Register (DRWCR)

WC15 <-> WC0
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Bus Address Register (DRBAR)

BA15 <-> BA1 0
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Status Register (DRCSR)

ERR NEX ATTN MAINT STATUS CYCLE RDY IE XAD FNCT GO
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
  • ERR - Error; set by NEX or ATTN
  • NEX - Nonexistent Memory; also write-to-zero
  • ATTN - Attention; signal from user's hardware which can be tested, or cause an interrupt (below)
  • MAINT - Maintenance
  • STATUS - Signals from user hardware
  • CYCLE - DMA cycle requested
  • RDY - DRV11-B is able to accept a new command; set by ERR or WCR overflow, cleared by GO
  • IE - Interrupt Enable - When set, allows setting RDY to cause an interrupt
  • XAD - Extended Address; extension of BAR
  • FNCT - Signals to user's hardware
  • GO - Enables DMA, sent to user's hardware

Output Buffer Register (DROUTBUF)

OUT15 <-> OUT0
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Input Buffer Register (INBUF)

IN15 <-> IN0
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Retrieved from "https://gunkies.org/w/index.php?title=DRV11-B_Direct_Memory_Access_Interface&oldid=22351"