Difference between revisions of "KDF11-A CPU"

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[[Image:KDF11-ATop.jpg|250px|thumb|right| CPU]]
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[[Image:KDF11-ATop.jpg|250px|thumb|right|KDF11-A CPU, with KTF11-A MMU chip]]
  
The '''KDF11-A CPU''' is [[PDP-11]] [[Central Processing Unit|CPU]] for the [[QBUS]]; it is a [[DEC card form factor|dual]]-width [[printed circuit board|card]], the M8186. It uses the same 'Fonz' [[F-11 chip set]] as the other [[KDF11 CPUs]].
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The '''KDF11-A CPU''' is a [[PDP-11]] [[Central Processing Unit|CPU]] for the [[QBUS]]; it is a [[DEC card form factor|dual]]-width [[printed circuit board|card]], the M8186. It uses the same 'Fonz' [[F-11 chip set]] as the other [[KDF11 CPUs]].
  
 
It contains only the basic CPU, unlike the other KDF-11's: no [[Read-only memory|ROM]], no [[asynchronous serial line]]s, etc. It does support the optional [[KTF11-A memory management chip]] and the [[KEF11-A floating point chip]], but not the [[KEF11-B]] [[PDP-11 Commercial Instruction Set]] (CIS); for higher performance [[floating point]], the [[FPF11 floating point processor]] may be used.
 
It contains only the basic CPU, unlike the other KDF-11's: no [[Read-only memory|ROM]], no [[asynchronous serial line]]s, etc. It does support the optional [[KTF11-A memory management chip]] and the [[KEF11-A floating point chip]], but not the [[KEF11-B]] [[PDP-11 Commercial Instruction Set]] (CIS); for higher performance [[floating point]], the [[FPF11 floating point processor]] may be used.
  
The first version of the KDF11-A (Revision A) only suppported 256 Kbytes of [[main memory]]; later versions supported up to 4 Mbytes (but their [[QBUS CPU ODT|ODT]]'s are limited to 256 Kbytes). In the later models, a bit in the [[PDP-11 Memory Management#Control|SSR3]] CPU [[register]] must be set to allow use of more than 256 Kbytes.
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The first version of the KDF11-A (Revision A) only suppported 256 Kbytes of [[main memory]]; later versions supported up to 4 Mbytes (but their [[QBUS CPU ODT|ODT]]'s [[address space]] is limited to 256 Kbytes). In the later models, a bit in the [[PDP-11 Memory Management#Control|SSR3]] CPU [[register]] must be set to allow use of more than 256 Kbytes.
  
 
==Configuration==
 
==Configuration==
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{{PDP-11}}
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==Further reading==
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* ''11/23 ECO Status'', [[MicroNote]] #104
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* ''MMU Configuration Jumpers'', MicroNote #102
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* ''Peripheral Compatibility with 11/23 Systems'', MicroNote #072
  
[[Category: PDP-11 Processors]]
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==External links==
[[Category:QBUS Processors]]
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* [http://www.bitsavers.org/pdf/dec/pdp11/1123/EK-KDF11-UG-PR2_Mar79.pdf KDF11-AA User's Guide] (EK-KDF11-UG-PR2)
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* [http://www.bitsavers.org/pdf/dec/pdp11/1123/MP00734_KDF11A_EngrDrws.pdf KDF11-A Field Maintenance Print Set] (MP00734)
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* [http://www.ibiblio.org/pub/academic/computer-science/history/pdp-11/hardware/micronotes/numerical/micronote17.txt LSI-11/23 ECO History] (uNote #017)
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[[Category: PDP-11 QBUS Processors]]

Latest revision as of 23:46, 31 July 2024

KDF11-A CPU, with KTF11-A MMU chip

The KDF11-A CPU is a PDP-11 CPU for the QBUS; it is a dual-width card, the M8186. It uses the same 'Fonz' F-11 chip set as the other KDF11 CPUs.

It contains only the basic CPU, unlike the other KDF-11's: no ROM, no asynchronous serial lines, etc. It does support the optional KTF11-A memory management chip and the KEF11-A floating point chip, but not the KEF11-B PDP-11 Commercial Instruction Set (CIS); for higher performance floating point, the FPF11 floating point processor may be used.

The first version of the KDF11-A (Revision A) only suppported 256 Kbytes of main memory; later versions supported up to 4 Mbytes (but their ODT's address space is limited to 256 Kbytes). In the later models, a bit in the SSR3 CPU register must be set to allow use of more than 256 Kbytes.

Configuration

A limited amount of configuration can be done with a number of jumpers in various locations (which differ depending on etch revision, with block of eleven in the middle of the card.Their functions are:

Jumper Function In Out
W1 Master Clock Enabled Disabled
W2 Reserved Factory Do not remove
W3 Unknown
W4 Event line Disabled Enabled
W5 Powerup option bit 1
W6 Powerup option bit 2
W7 Halt enable Halt Trap to 4
W8 Bootstrap address 0173000 Yes W9-W15
W09 Bootstrap address bit 9 1 0
W10 Bootstrap address bit 10 1 0
W11 Bootstrap address bit 11 1 0
W12 Bootstrap address bit 12 1 0
W13 Bootstrap address bit 13 1 0
W14 Bootstrap address bit 14 1 0
W15 Bootstrap address bit 15 1 0
W16 Reserved Factory Do not remove
W17 Reserved Factory Do not remove
W18 Wakeup circuit Disabled Enabled

Powerup options are:

W6 W5 Action
Out Out PC from 024, PS from 026
Out In ODT
In Out PC=configuration jumpers
In In Extended microcode (trap to 010 if none)

Further reading

  • 11/23 ECO Status, MicroNote #104
  • MMU Configuration Jumpers, MicroNote #102
  • Peripheral Compatibility with 11/23 Systems, MicroNote #072

External links