Difference between revisions of "ME10 core memory"
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| − | The '''ME10''' was a [[core memory|core]] [[main memory]] system for the mid-period [[PDP-10]]s, principally the [[KI10]]. It connected to the so-called external memory bus of either the 18-bit or 22-bit [[address]] form; address bits 14-17 can be set to 'ignore' when an ME10 is connected to a [[KA10]], which uses the 18-bit bus version. [[Parity]] is provided to protect the memory contents. An ME10 contained 16KW; it had an [[access time]] of .55 µseconds (maximum .61 µseconds) and a [[cycle time]] of 1.0 µseconds. | + | The '''ME10''' was a [[core memory|core]] [[main memory]] system for the mid-period [[PDP-10]]s, principally the [[KI10]]. It connected to the so-called [[PDP-10 Memory Bus|external memory bus]] of either the 18-bit or 22-bit [[address]] form; address bits 14-17 can be set to 'ignore' when an ME10 is connected to a [[KA10]], which uses the 18-bit bus version. [[Parity]] is provided to protect the memory contents. An ME10 contained 16KW; it had an [[access time]] of .55 µseconds (maximum .61 µseconds) and a [[cycle time]] of 1.0 µseconds. |
It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s. | It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s. | ||
| − | Each port could be independently set for its address, and for either 2- or 4-way [[interleaving]] (using [[address]] bits 21 and 35, and bits 20 and 34, respectively; recall that the PDP-10 uses [[big-endian]] numbering, so bit 35 is the low-order bit). | + | Each port could be independently set for its address, and for either 2- or 4-way [[memory interleaving|interleaving]] (using [[address]] bits 21 and 35, and bits 20 and 34, respectively; recall that the PDP-10 uses [[big-endian]] numbering, so bit 35 is the low-order bit). |
[[Category: PDP-10 Memories]] | [[Category: PDP-10 Memories]] | ||
Latest revision as of 12:55, 2 August 2023
The ME10 was a core main memory system for the mid-period PDP-10s, principally the KI10. It connected to the so-called external memory bus of either the 18-bit or 22-bit address form; address bits 14-17 can be set to 'ignore' when an ME10 is connected to a KA10, which uses the 18-bit bus version. Parity is provided to protect the memory contents. An ME10 contained 16KW; it had an access time of .55 µseconds (maximum .61 µseconds) and a cycle time of 1.0 µseconds.
It was a multi-port memory, with 4 ports per memory system: each port can be independently disabled. The CPU uses one port (in a multi-processor system, one per CPU); the others are used by channels (such as a DF10) for mass storage such as disks.
Each port could be independently set for its address, and for either 2- or 4-way interleaving (using address bits 21 and 35, and bits 20 and 34, respectively; recall that the PDP-10 uses big-endian numbering, so bit 35 is the low-order bit).
