Difference between revisions of "Maxc"
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[[Image:Maxc.jpg|300px|right|thumb|Xerox Maxc]] | [[Image:Maxc.jpg|300px|right|thumb|Xerox Maxc]] | ||
| − | '''Maxc1''' and '''Maxc2''' ( | + | '''Maxc1''' and '''Maxc2''' (originally capitalized '''MAXC''' - an acronym for 'Multiple Access Xerox Computer') were a pair of [[PDP-10]] clones made at [[Xerox PARC]], after the Xerox corporate level objected to the acquisition of machines from outside the company, instead of from Xerox's subsidiary, Xerox Data Systems - [[Scientific Data Systems]] before it was acquired by Xerox. (They chose the PDP-10 as they wanted to be able to run [[INTERLISP]].) |
They were [[microcode]]d machines, using an 72-bit [[instruction|microinstruction]]. They contained 2K [[word]]s of microcode, and microinstructions executed in 200 nsec (Maxc1); 4K words, at 150 nsec (Maxc2). The hardware supported up to 16 levels of [[subroutine]] calls in the microcode. This capability was used to support bulk data transfers (from [[disk]] [[mass storage]]); a technique which was later used in the [[Xerox Alto|Alto]]. | They were [[microcode]]d machines, using an 72-bit [[instruction|microinstruction]]. They contained 2K [[word]]s of microcode, and microinstructions executed in 200 nsec (Maxc1); 4K words, at 150 nsec (Maxc2). The hardware supported up to 16 levels of [[subroutine]] calls in the microcode. This capability was used to support bulk data transfers (from [[disk]] [[mass storage]]); a technique which was later used in the [[Xerox Alto|Alto]]. | ||
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The [[main memory]] was built out of then-novel [[Dynamic RAM|DRAM]] [[integrated circuit|chips]] from [[Intel]], the new [[Intel 1103]] 1Kx1 chip. It used [[error-correcting code|ECC]] to produce reliable memory; with a [[word]] length of 48 bits (compared to the PDP-10's native length of 36 bits; only 7 of the extra 12 bits were used for the ECC), it could correct all single-bit errors, and detect (but not correct) double-bit errors. Thus, single failed chips could be ignored, and replaced during scheduled maintenance. | The [[main memory]] was built out of then-novel [[Dynamic RAM|DRAM]] [[integrated circuit|chips]] from [[Intel]], the new [[Intel 1103]] 1Kx1 chip. It used [[error-correcting code|ECC]] to produce reliable memory; with a [[word]] length of 48 bits (compared to the PDP-10's native length of 36 bits; only 7 of the extra 12 bits were used for the ECC), it could correct all single-bit errors, and detect (but not correct) double-bit errors. Thus, single failed chips could be ignored, and replaced during scheduled maintenance. | ||
| − | They ran the [[TENEX]] [[operating system]]; to do this, Maxc implemented [[virtual memory]] mechanisms comparable to those added to the [[KA10]] by [[ | + | They ran the [[TENEX]] [[operating system]]; to do this, Maxc implemented [[virtual memory]] mechanisms comparable to those added to the [[KA10]] by the [[BBN Pager]], including a 1024x18 bit mapping memory. Both Maxc machines also supported [[PARC Universal Packet|PUP]]. |
Maxc1 was built during the period from February 1971 to April 1973; it was de-commissioned early in 1981. Maxc2 was built between June 1975 and April 1977. | Maxc1 was built during the period from February 1971 to April 1973; it was de-commissioned early in 1981. Maxc2 was built between June 1975 and April 1977. | ||
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**** [https://xeroxparcarchive.computerhistory.org/indigo/maxc/MaxcOperations0-24Press.Dm!3_/.MaxcOps0.Press.pdf Maxc Operations] - [https://raw.githubusercontent.com/PDP-10/maxc/master/pdf/MaxcOperations0-24.press.pdf All files in one document] | **** [https://xeroxparcarchive.computerhistory.org/indigo/maxc/MaxcOperations0-24Press.Dm!3_/.MaxcOps0.Press.pdf Maxc Operations] - [https://raw.githubusercontent.com/PDP-10/maxc/master/pdf/MaxcOperations0-24.press.pdf All files in one document] | ||
*** [https://raw.githubusercontent.com/PDP-10/maxc/master/pdf/Maxc-room.pdf Maxc machine room] | *** [https://raw.githubusercontent.com/PDP-10/maxc/master/pdf/Maxc-room.pdf Maxc machine room] | ||
| + | * [https://www.digibarn.com/collections/parts/maxc-board/ Original boards from a Xerox MAXC Time Sharing System] | ||
[[Category: PDP-10 Systems]] | [[Category: PDP-10 Systems]] | ||
[[Category: Xerox Mainframes]] | [[Category: Xerox Mainframes]] | ||
| + | [[Category: Unique Computers]] | ||
Latest revision as of 00:43, 17 February 2024
Maxc1 and Maxc2 (originally capitalized MAXC - an acronym for 'Multiple Access Xerox Computer') were a pair of PDP-10 clones made at Xerox PARC, after the Xerox corporate level objected to the acquisition of machines from outside the company, instead of from Xerox's subsidiary, Xerox Data Systems - Scientific Data Systems before it was acquired by Xerox. (They chose the PDP-10 as they wanted to be able to run INTERLISP.)
They were microcoded machines, using an 72-bit microinstruction. They contained 2K words of microcode, and microinstructions executed in 200 nsec (Maxc1); 4K words, at 150 nsec (Maxc2). The hardware supported up to 16 levels of subroutine calls in the microcode. This capability was used to support bulk data transfers (from disk mass storage); a technique which was later used in the Alto.
In addition to a PDP-10-compatible mode, Maxc microcode also implemented a Byte Lisp mode with 9-bit instructions specially tailored for LISP. The INTERLISP compiler and runtime has support for this instruction set under a Maxc condition, and the Maxc monitor has special JSYS calls to facilitate Byte Lisp code.
A front end (a Data General Nova on Maxc1, and an Alto on Maxc2) was used to load and debug the microcode; all the input/output peripherals other than the disks were also connected to the front end.
The main memory was built out of then-novel DRAM chips from Intel, the new Intel 1103 1Kx1 chip. It used ECC to produce reliable memory; with a word length of 48 bits (compared to the PDP-10's native length of 36 bits; only 7 of the extra 12 bits were used for the ECC), it could correct all single-bit errors, and detect (but not correct) double-bit errors. Thus, single failed chips could be ignored, and replaced during scheduled maintenance.
They ran the TENEX operating system; to do this, Maxc implemented virtual memory mechanisms comparable to those added to the KA10 by the BBN Pager, including a 1024x18 bit mapping memory. Both Maxc machines also supported PUP.
Maxc1 was built during the period from February 1971 to April 1973; it was de-commissioned early in 1981. Maxc2 was built between June 1975 and April 1977.
Further reading
- Michael A. Hiltzik, Dealers of Lightning: Xerox PARC and the Dawn of the Computer Age, HarperBusiness, New York, 1999 - pp. 99-116
External links
- The Maxc Systems - good, detailed paper by Edward R. Fiala of PARC, one of the builders
- MAXC - MAXC documents at BitSavers
- Pictures - images of the machine; internals, under construction, and finished
- Maxc Operations
- The MAXC Microprocessor
- A LISP Machine with Very Compact Programs, L. Peter Deutsch, 1973.
- Monitor - Maxc monitor sources (and other files related to PUP)]
- Xerox PARC Alto filesystem archive
- Original boards from a Xerox MAXC Time Sharing System
