Difference between revisions of "Power 6/32"

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(→‎Instruction Set: Explain 'indexed' addressing mode; note emulated instructions)
(→‎Opcode table: Add number of operands for all instrs)
 
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===Opcode table===
 
===Opcode table===
  
−
The opcode map and mnemonics for the [[assembly language|assembler]] are as follows:
+
The opcode map and mnemonics for the [[instruction set]] in the 4.3 BSD [[assembly language|assembler]], along with the number of operands for each instruction (if any) are as follows:
  
 
{| class="wikitable"
 
{| class="wikitable"
−
! || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || a || b || c || d || e ||f
+
!   !! 0 !! 1 !! 2 !! 3 !!    4    !! 5 !! 6 !! 7
 
|-
 
|-
−
! 0x00
+
| '''0x00''' || halt ||   ||   ||   ||   || sinf || ldf - 1 || ldd - 1
−
| halt   || -      || -      || -      || -      || sinf   || ldf     || ldd     || addb2  || movb    || addw2  || movw    || addl2  || movl    || bbs    || -    
 
 
|-
 
|-
−
! 0x10
+
| '''0x10''' || nop || brb - 1 ||   || brw - 1 ||   || cosf || lnf - 1 || lnd - 1
−
| nop     || brb     || -      || brw     || -      || cosf   || lnf     || lnd     || addb3  || cmpb    || addw3  || cmpw    || addl3  || cmpl    || bbc    || -    
 
 
|-
 
|-
−
! 0x20
+
| '''0x20''' || rei || bneq/bnequ - 1 ||   || cvtwl - 2 ||   || atanf || stf - 1 || std - 1
−
| rei     || bneq/bnequ || -      || cvtwl   || -      || atanf   || stf     || std     || subb2  || mcomb  || subw2  || mcomw  || subl2  || mcoml  || emul    || aoblss
 
 
|-
 
|-
−
! 0x30
+
| '''0x30''' || bpt || beql/beqlu - 1 ||   || cvtwb - 2 ||   || logf || cmpf - 1 || cmpd - 1
−
| bpt     || beql/beqlu || -      || cvtwb   || -      || logf   || cmpf   || cmpd   || subb3  || bitb    || subw3  || bitw    || subl3  || bitl    || ediv    || aobleq
 
 
|-
 
|-
−
! 0x40
+
| '''0x40''' || ret || bgtr - 1 ||   ||   ||   || sqrtf || cmpf2 - 2|| cmpd2 - 2
−
| ret     || bgtr   || -      || -      || -      || sqrtf   || cmpf2   || cmpd2   || shll    || clrb    || shlq    || clrw    || mull2  || clrl    || shal    || -    
 
 
|-
 
|-
−
! 0x50
+
| '''0x50''' ||   || bleq - 1 ||   ||   ||   || expf || tstf || tstd
−
| -      || bleq   || -      || -      || -      || expf   || tstf   || tstd   || shrl    || tstb    || shrq    || tstw    || mull3  || tstl    || shar    || bbssi 
 
 
|-
 
|-
−
! 0x60
+
| '''0x60''' || ldpctx ||   ||   ||   ||   ||   ||   || pushd
−
| ldpctx || -      || -      || -      || -      || -      || -      || pushd   || -      || incb    || -      || incw    || divl2  || incl    || -      || cvtlb 
 
 
|-
 
|-
−
! 0x70
+
| '''0x70''' || svpctx || jmp - 1 ||   ||   ||   ||   || cvlf - 1 || cvld - 1
−
| svpctx || jmp     || -      || -      || -      || -      || cvlf   || cvld   || -      || decb    || -       || decw    || divl3  || decl    || -      || cvtlw 
 
 
|-
 
|-
−
! 0x80
+
| '''0x80''' ||   || bgeq - 1 || movs2 ||   ||   ||   || cvfl - 1 || cvdl - 1
−
| -      || bgeq   || movs2   || -      || -      || -      || cvfl   || cvdl   || orb2    || cvtbl  || orw2    || bispsw  || orl2    || adwc    || adda    || -    
 
 
|-
 
|-
−
! 0x90
+
| '''0x90''' ||   || blss - 1 || cmps2 ||   ||   ||   ||   || ldfd - 1
−
| -      || blss   || cmps2   || -      || -      || -      || -      || ldfd   || orb3    || cvtbw  || orw3    || bicpsw  || orl3    || sbwc    || suba    || -    
 
 
|-
 
|-
−
! 0xa0
+
| '''0xA0''' ||   || bgtru - 1 ||   ||   ||   ||   || cvdf ||  
−
| -      || bgtru  || -      || -       || -      || -      || cvdf    || -      || andb2  || movzbl  || andw2  || loadr  || andl2  || mtpr    || ffs    || -     
 
 
|-
 
|-
−
! 0xb0
+
| '''0xB0''' ||   || blequ - 1 ||   ||   ||   ||   || negf || negd
−
| -      || blequ   || -      || -      || -      || -      || negf   || negd   || andb3  || movzbw  || andw3  || storer  || andl3  || mfpr    || ffc    || calls 
 
 
|-
 
|-
−
! 0xc0
+
| '''0xC0''' || prober - 3 || bvc - 1 || movs3 || movzwl - 2 ||   ||   || addf - 1 || addd - 1
−
| prober || bvc     || movs3   || movzwl || -      || -      || addf   || addd   || xorb2  || movob  || xorw2  || movow  || xorl2  || movpsl  || btcs    || kcall 
 
 
|-
 
|-
−
! 0xd0
+
| '''0xD0''' || probew - 3 || bvs - 1 || cmps3 ||   ||   ||   || subf - 1 || subd - 1
−
| probew || bvs     || cmps3   || -      || -      || -      || subf   || subd   || xorb3  || pushb  || xorw3  || pushw  || xorl3  || pushl  || -      || -    
 
 
|-
 
|-
−
! 0xe0
+
| '''0xE0''' || insque - 2 || bgequ/bcs - 1 ||   ||   ||   ||   || mulf - 1 || muld - 1
−
| insque || bgequ/bcs || -      || -      || -      || -      || mulf   || muld   || mnegb  || movab  || mnegw  || movaw  || mnegl  || moval  || -      || -    
 
 
|-
 
|-
−
! 0xf0
+
| '''0xF0''' || remque - 1 || bcc/blssu - 1 ||   ||   ||   ||   || divf - 1 || divd - 1
−
| remque || bcc/blssu || -       || -       || -       || -       || divf    || divd    || movblk || pushab || -      || pushaw || casel   || pushal || callf   || -
+
|}
 +
 
 +
{| class="wikitable"
 +
!   !! 8 !! 9 !! A !! B !! C !! D !! E !! F
 +
|-
 +
| '''0x00''' || addb2 - 2|| movb - 2 || addw2 - 2|| movw - 2 || addl2 - 2|| movl - 2 || bbs - 3 ||  
 +
|-
 +
| '''0x10''' || addb3 - 3 || cmpb - 2 || addw3 - 3 || cmpw - 2 || addl3 - 3 || cmpl - 2 || bbc - 3 ||  
 +
|-
 +
| '''0x20''' || subb2 - 2|| mcomb - 2 || subw2 - 2|| mcomw - 2 || subl2 - 2|| mcoml - 2 || emul - 4 || aoblss - 3
 +
|-
 +
| '''0x30''' || subb3 - 3 || bitb - 2 || subw3 - 3 || bitw - 2 || subl3 - 3 || bitl - 2 || ediv - 4 || aobleq - 3
 +
|-
 +
| '''0x40''' || shll - 3 || clrb - 1 || shlq - 3 || clrw - 1 || mull2 - 2|| clrl - 1 || shal - 3
 +
|-
 +
| '''0x50''' || shrl - 3 || tstb - 1 || shrq - 3 || tstw - 1 || mull3 - 3 || tstl - 1 || shar - 3 || bbssi - 3
 +
|-
 +
| '''0x60''' ||   || incb - 1 ||   || incw - 1 || divl2 - 2|| incl - 1 ||   || cvtlb - 2
 +
|-
 +
| '''0x70''' ||   || decb - 1 ||   || decw - 1 || divl3 - 3 || decl - 1 ||   || cvtlw - 2
 +
|-
 +
| '''0x80''' || orb2 - 2|| cvtbl - 2 || orw2 - 2|| bispsw - 1 || orl2 - 2|| adwc - 2 || adda - 2 ||  
 +
|-
 +
| '''0x90''' || orb3 - 3 || cvtbw - 2 || orw3 - 3 || bicpsw - 1 || orl3 - 3 || sbwc - 2 || suba - 2 ||  
 +
|-
 +
| '''0xA0''' || andb2 - 2|| movzbl - 2 || andw2 - 2|| loadr - 2 || andl2 - 2|| mtpr - 2 || ffs - 2 ||  
 +
|-
 +
| '''0xB0''' || andb3 - 3 || movzbw - 2 || andw3 - 3 || storer - 2 || andl3 - 3 || mfpr - 2 || ffc - 2 || calls - 2
 +
|-
 +
| '''0xC0''' || xorb2 - 2|| movob - 2 || xorw2 - 2|| movow - 2 || xorl2 - 2|| movpsl - 1 || btcs - 1 || kcall - 1
 +
|-
 +
| '''0xD0''' || xorb3 - 3 || pushb - 1 || xorw3 - 3 || pushw - 1 || xorl3 - 3 || pushl - 1 ||   ||  
 +
|-
 +
| '''0xE0''' || mnegb - 2 || movab - 2 || mnegw - 2 || movaw - 2 || mnegl - 2 || moval - 2 ||   ||  
 +
|-
 +
| '''0xF0''' || movblk || pushab - 1 ||   || pushaw - 1 || casel - 3 || pushal - 1 || callf - 2 ||  
 
|}
 
|}
  

Latest revision as of 04:49, 26 December 2024

3D rendering by a Power 6/32 in Young Sherlock Holmes

The Power 6/32, code named Tahoe, from Computer Consoles Incorporated, was a supermini; it used the VERSAbus as its bus. It is most noted from the CSRG porting 4.3 BSD to it, in the 4.3 BSD Tahoe release.

Although it was not very successful commercially (in part because CCI exited the computer business shortly after it was released), it was very influential as the first non-VAX machine that BSD UNIX was ported to. The Tahoe did help separate out a lot of VAX-specific code from the base, allowing BSD to become more portable, but the Power 6/32 machine quickly disappeared off the market, and not much is known about them.

The CPU was re-sold (under other names) in systems from several vendors (viewed by CCI as OEMs): Unisys sold the 6/32 under the name 'Unisys 7000/40', using their own bastardized BSD+SYSV Unix. (Kuwait Petroleum in Denmark had one of them.) ICL had the 'Clan 7'. Harris had the HCX-5, -7, and -9 models (for which a small amount of information survives - below), running the SysV derivative HCX/UX.

Pixar used a Power 6/32 to render the stained-glass knight in the 1985 movie Young Sherlock Holmes.

Details

The Power 6/32 CPU was implemented in TTL; it had a clock rate of 100nS.

The performance is given in this table, from dhrystone.c (below): 

 *----------------DHRYSTONE VERSION 1.0 RESULTS BEGIN--------------------------
 *
 * MACHINE      MICROPROCESSOR  OPERATING       COMPILER        DHRYSTONES/SEC.
 * TYPE                         SYSTEM                          NO REG  REGS
 * --------------------------   ------------    -----------     ---------------
 * CCI POWER 6/32               COS(SV+4.2)     cc              7500    7800
 * CCI POWER 6/32               POWER 6 UNIX/V  cc              8236    8498
 * CCI POWER 6/32               4.2 Rel. 1.2b   cc              8963    9544
 * VAX 11/780   -               UNIX 5.2        cc              1515    1562
 * VAX 11/780   -               UNIX 4.3bsd     cc              1646    1662

Which may give some indication on the initial reasons why the Power 6/32 was chosen as the successor to the VAX by CSRG.

Instruction Set

Although apparently no documentation survives and is accessible, we can infer a lot from the instruction decoding/printing routines in the debuggers from 4.3 BSD Tahoe, and their input file 'instrs' (below).

  • Instructions start with a 1-byte opcode, and, depending on the opcode and 'addressing mode' (below), are followed by a basic set of 0-3 operands. (Two instructions, 'ediv' and 'emul', take 4 operands; if any operand uses the 'indexed' addressing mode, an extra operand is required for each such use.)
  • Operands start with 1 byte, containing 4 bits of 'addressing mode' and 4 bits of 'register':
    • The CPU has sixteen 32-bit registers r0 ... r13 (fp), r14 (sp), r15 (pc).
    • The addressing modes (reminiscent of those of the PDP-11), and their encodings, are:
Encoding Mode notation
0x0 short literals 0-15  
0x1 short literals 16-31
0x2 short literals 32-47
0x3 short literals 48-63
0x4 indexed [r]
0x5 register immediate r
0x6 register deferred (r)
0x7 auto-decrement -(r)
0x8 auto-increment (r)+
0x9 auto-increment deferred *(r)+
0xA byte displacement BD(r)
0xB byte displacement deferred *BD(r)
0xC short-word displacement WD(r)
0xD short-word displacement deferred *WD(r)
0xE long-word displacement LD(r)
0xF long-word displacement deferred *LD(r)
The "indexed" mode apparently adds the contents of the named register to the address generated by the following operand. (It likely cannot be used with the "register immediate" addressing mode.)
For operands of the 6 'displacement' modes, the operand is followed by a value of the indicated length.

Opcode table

The opcode map and mnemonics for the instruction set in the 4.3 BSD assembler, along with the number of operands for each instruction (if any) are as follows:

  0 1 2 3    4    5 6 7
0x00 halt         sinf ldf - 1 ldd - 1
0x10 nop brb - 1   brw - 1   cosf lnf - 1 lnd - 1
0x20 rei bneq/bnequ - 1   cvtwl - 2   atanf stf - 1 std - 1
0x30 bpt beql/beqlu - 1   cvtwb - 2   logf cmpf - 1 cmpd - 1
0x40 ret bgtr - 1       sqrtf cmpf2 - 2 cmpd2 - 2
0x50   bleq - 1       expf tstf tstd
0x60 ldpctx             pushd
0x70 svpctx jmp - 1         cvlf - 1 cvld - 1
0x80   bgeq - 1 movs2       cvfl - 1 cvdl - 1
0x90   blss - 1 cmps2         ldfd - 1
0xA0   bgtru - 1         cvdf  
0xB0   blequ - 1         negf negd
0xC0 prober - 3 bvc - 1 movs3 movzwl - 2     addf - 1 addd - 1
0xD0 probew - 3 bvs - 1 cmps3       subf - 1 subd - 1
0xE0 insque - 2 bgequ/bcs - 1         mulf - 1 muld - 1
0xF0 remque - 1 bcc/blssu - 1         divf - 1 divd - 1
  8 9 A B C D E F
0x00 addb2 - 2 movb - 2 addw2 - 2 movw - 2 addl2 - 2 movl - 2 bbs - 3  
0x10 addb3 - 3 cmpb - 2 addw3 - 3 cmpw - 2 addl3 - 3 cmpl - 2 bbc - 3  
0x20 subb2 - 2 mcomb - 2 subw2 - 2 mcomw - 2 subl2 - 2 mcoml - 2 emul - 4 aoblss - 3
0x30 subb3 - 3 bitb - 2 subw3 - 3 bitw - 2 subl3 - 3 bitl - 2 ediv - 4 aobleq - 3
0x40 shll - 3 clrb - 1 shlq - 3 clrw - 1 mull2 - 2 clrl - 1 shal - 3
0x50 shrl - 3 tstb - 1 shrq - 3 tstw - 1 mull3 - 3 tstl - 1 shar - 3 bbssi - 3
0x60   incb - 1   incw - 1 divl2 - 2 incl - 1   cvtlb - 2
0x70   decb - 1   decw - 1 divl3 - 3 decl - 1   cvtlw - 2
0x80 orb2 - 2 cvtbl - 2 orw2 - 2 bispsw - 1 orl2 - 2 adwc - 2 adda - 2  
0x90 orb3 - 3 cvtbw - 2 orw3 - 3 bicpsw - 1 orl3 - 3 sbwc - 2 suba - 2  
0xA0 andb2 - 2 movzbl - 2 andw2 - 2 loadr - 2 andl2 - 2 mtpr - 2 ffs - 2  
0xB0 andb3 - 3 movzbw - 2 andw3 - 3 storer - 2 andl3 - 3 mfpr - 2 ffc - 2 calls - 2
0xC0 xorb2 - 2 movob - 2 xorw2 - 2 movow - 2 xorl2 - 2 movpsl - 1 btcs - 1 kcall - 1
0xD0 xorb3 - 3 pushb - 1 xorw3 - 3 pushw - 1 xorl3 - 3 pushl - 1    
0xE0 mnegb - 2 movab - 2 mnegw - 2 movaw - 2 mnegl - 2 moval - 2    
0xF0 movblk pushab - 1   pushaw - 1 casel - 3 pushal - 1 callf - 2  

A number of the more complex arithmetic instructions, many of them the floating point and the trigonometric ones (CVLF, CVLD, CVFL, CVDL, LDFD, CVDF, ADDF, ADDD, SUBF, SUBD, MULF, MULD, DIVF, DIVD, SINF, COSF, ATANF, LOGF, SQRTF and EXPF), do not seem to be implemented in the Power 6/32; instead, they were emulated in software, after an attempt to execute them resulted in a trap.

See also

External links

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