Difference between revisions of "DR11-A General Device Interface"
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==Registers== | ==Registers== | ||
| − | The device has three control and [[buffer]] [[register]]s, which can be configured to any three sequential [[word]] locations in the I/O page; the first DR11-A is normally configured to [[address]]es | + | The device has three control and [[buffer]] [[register]]s, which can be configured to any three sequential [[word]] locations in the I/O page; the first DR11-A is normally configured to [[address]]es 777520-777524: |
{| border=1 | {| border=1 | ||
! Register !! Abbreviation !! Address | ! Register !! Abbreviation !! Address | ||
|- | |- | ||
| − | |Control and Status Register || DRCSR || | + | |Control and Status Register || DRCSR || 777520 |
|- | |- | ||
| − | |Output Buffer Register || DROUTBUF || | + | |Output Buffer Register || DROUTBUF || 777522 |
|- | |- | ||
| − | |Input Buffer Register || DRINBUF || | + | |Input Buffer Register || DRINBUF || 777524 |
|} | |} | ||
Revision as of 15:00, 20 December 2018
The DR11-A General Device Interface was a UNIBUS device controller which provided a pair of 16-bit parallel ports, one input, and one output.
It was a dual format card (M786), along with two standard single-width card FLIP CHIPs, the M105 Address Selector and the M782 Interrupt Control; they used an SPC slot.
Connection to the user's device is via a DEC backplane slot connector on one side of the card, into which two single-width paddle cards plugged.
The DR11-A was replaced by the single-board DR11-C general device interface. The DR11-C is upwardly compatible with the DR11-A for programming, but uses the cheaper and easier to work with Berg connectors.
Contents
Registers
The device has three control and buffer registers, which can be configured to any three sequential word locations in the I/O page; the first DR11-A is normally configured to addresses 777520-777524:
| Register | Abbreviation | Address |
|---|---|---|
| Control and Status Register | DRCSR | 777520 |
| Output Buffer Register | DROUTBUF | 777522 |
| Input Buffer Register | DRINBUF | 777524 |
In the register contents (below), bits which are read/write or unused are shown in normal font, those which are read-only are in italics.
Status Register (DRCSR)
| REQ B | Unused | REQ A | INT ENB A | INT ENB B | Unused | |||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
Output Buffer Register (DROUTBUF)
| OUT15 <-> OUT0 | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
Input Buffer Register (INBUF)
| IN15 <-> IN0 | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
