Difference between revisions of "LSI-11 CPUs"
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| − | The '''LSI-11 CPUs''' were DEC's first cost-reduced [[PDP-11]] [[Central Processing Unit|CPUs]], | + | The '''LSI-11 CPUs''' were DEC's first cost-reduced [[PDP-11]] [[Central Processing Unit|CPUs]], using a [[microprocessor]] (the [[LSI-11 chip set]]). They also used a new [[bus]], the [[QBUS]]; and used [[QBUS CPU ODT|ODT]] for control. |
The first [[LSI-11]] was a [[DEC card form factor|quad]] board (M7264) with additional functionality on-board. A later board, the [[LSI-11/2]], packaged just the CPU on a dual card. | The first [[LSI-11]] was a [[DEC card form factor|quad]] board (M7264) with additional functionality on-board. A later board, the [[LSI-11/2]], packaged just the CPU on a dual card. | ||
Revision as of 19:09, 19 August 2019
The LSI-11 CPUs were DEC's first cost-reduced PDP-11 CPUs, using a microprocessor (the LSI-11 chip set). They also used a new bus, the QBUS; and used ODT for control.
The first LSI-11 was a quad board (M7264) with additional functionality on-board. A later board, the LSI-11/2, packaged just the CPU on a dual card.
Both LSI-11s are Q16 devices; they only drive 16 address lines. Although they can be plugged into a Q18 or Q22 backplane, they will only function with Q16 main memory. (With Q22 memory, the pins used for BDAL18-21 are used for other, internal signals by the LSI-11. The reason for the incompatability with Q18 memory is currently unknown.)
There were CPU options were available for the LSI-11s: the KEV11-A, for the EIS/FIS instructions; the KEV11-B provides EIS without FIS; the KEV11-C provides a subset of the PDP-11 CIS (it also apparently includes the EIS, but not the FIS).
They also supported the optional KUV11 Writeable Control Store.
