Difference between revisions of "KE11-F Floating Instruction Set"
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==External links== | ==External links== | ||
| − | * [http://bitsavers.org/pdf/dec/pdp11/1140/KE11_RefMan.pdf KE11-E and KE11-F instruction set options user's manual] | + | * [http://www.bitsavers.org/pdf/dec/pdp11/1140/KE11_RefMan.pdf KE11-E and KE11-F instruction set options user's manual] (EK-KE11E-OP-001) <!-- also http://www.bitsavers.org/www.computer.museum.uq.edu.au/pdf/EK-KE11E-OP-001%20KE11-E%20and%20KE11-F%20Instruction%20Set%20Options%20User's%20Manual.pdf --> |
* [http://www.bitsavers.org/www.computer.museum.uq.edu.au/pdf/EK-KE11E-TM-002%20KE11-E%20and%20KE11-F%20Instruction%20Set%20Options%20Manual.pdf KE11-E and KE11-F instruction set options manual] (EK-KE11E-TM-002) | * [http://www.bitsavers.org/www.computer.museum.uq.edu.au/pdf/EK-KE11E-TM-002%20KE11-E%20and%20KE11-F%20Instruction%20Set%20Options%20Manual.pdf KE11-E and KE11-F instruction set options manual] (EK-KE11E-TM-002) | ||
* [https://manx-docs.org/collections/hcps/KE11-FIS.pdf KE11-F floating instruction set (FIS) option engineering drawings] | * [https://manx-docs.org/collections/hcps/KE11-FIS.pdf KE11-F floating instruction set (FIS) option engineering drawings] | ||
[[Category: PDP-11 Processors]] | [[Category: PDP-11 Processors]] | ||
Revision as of 18:01, 19 November 2021
The KE11-F Floating Instruction Set is the optional floating point unit for the KD11-A CPU of the PDP-11/40. It implements the PDP-11 FIS floating point, not the full FP11 floating point.
Physically, it consists of a single quad board, the M7239, which plugs into a pre-wired slot in the CPU backplane.
It requires the installation of the KE11-E Extended Instruction Set, which allows the microcode of the basic CPU to be extended.
The KE11-F includes its own microcode ROM, which provides an additional 8 bits width of microcode (to control the data paths and registers on the M7239), but it also uses microcode stored on the KE11-E, to control registers and data paths elsewhere.
