KE11-F Floating Instruction Set: Difference between revisions
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* [https://manx-docs.org/collections/hcps/KE11-FIS.pdf KE11-F floating instruction set (FIS) option engineering drawings] | * [https://manx-docs.org/collections/hcps/KE11-FIS.pdf KE11-F floating instruction set (FIS) option engineering drawings] | ||
[[Category: PDP-11 Processors]] | [[Category: PDP-11 UNIBUS Processors]] | ||
Revision as of 00:34, 12 October 2022
The KE11-F Floating Instruction Set is the optional floating point unit for the KD11-A CPU of the PDP-11/40. It implements the PDP-11 FIS floating point, not the full FP11 floating point.
Physically, it consists of a single quad board, the M7239, which plugs into a pre-wired slot in the CPU backplane.
It requires the installation of the KE11-E Extended Instruction Set, which allows the microcode of the basic CPU to be extended.
The KE11-F includes its own microcode ROM, which provides an additional 8 bits width of microcode (to control the data paths and registers on the M7239), but it also uses microcode stored on the KE11-E, to control registers and data paths elsewhere.
