Difference between revisions of "MSV11-J memory module"
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[[Image:M8637.jpg|150px|right]] | [[Image:M8637.jpg|150px|right]] | ||
| − | The '''MSV11-J''' (M8637) is a [[QBUS]] [[main memory]] card; it holds up to | + | The '''MSV11-J''' (M8637) is a [[QBUS]]/[[Private Memory Interconnect|PMI]] [[Dynamic RAM|DRAM]] [[main memory]] card. As a PMI card, it uses the [[CD interconnect]]; it can therefore ''only'' be plugged into a [[QBUS#Backplanes|Q/CD backplane]]. '''''NOTE:''''' Plugging an MSV11-J card into a regular [[QBUS#Backplanes|Q/Q backplane]] will '''damage''' the MSV11-J. |
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| + | It has [[Error-correcting code|ECC]] which automagically corrects single-[[bit]] errors (at a slight penalty in response time), and detects double-bit errors. It holds up to 2 Mbyes when fully populated with 256Kx1 DRAM [[integrated circuit|chips]], or 1 Mbyte when half-populated (the only partially-filled configuration supported). It supports block mode on both the QBUS and PMI. | ||
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| + | Although it can function in QBUS-only mode (but see the note below about the -JB and -JC versions), it is really intended for use with a PMI-capable [[Central Processing Unit|CPU]], such as the [[KDJ11-B CPU|KDJ11-B]]. In systems such as the [[PDP-11/83]], where the primary [[Input/output|I/O]] [[bus]] is the QBUS, the card 'speaks' PMI to the CPU, and QBUS to the devices. In the [[PDP-11/84]], the PMI is used for communication with both the CPU and the [[KTJ11-B UNIBUS adapter]]. | ||
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| + | The memory is arranged as 2 banks, each 16 data bits wide, with 6 additional bits for the ECC. One bank is used to hold [[word]]s at even locations, the other for those in odd; a read cycle from the bus will read both sides simultaneously, and so when in PMI mode, the second word is already available once the first has been sent. | ||
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| + | On power-on, the system is frozen (via negation of the BPOK QBUS signal) while the memory is cleared, to prevent spurious ECC errors. For [[diagnostic]] purposes, the ECC can be disabled, and there are also means for the CPU to read/write the ECC bits directly. | ||
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| + | Four versions exist: | ||
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| + | * MSV11-JB, 1 Mbyte | ||
| + | * MSV11-JC, 2 Mbyte | ||
| + | * MSV11-JD, 1 Mbyte | ||
| + | * MSV11-JE, 2 Mbyte | ||
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| + | The -JB and -JC are earlier versions which contain an error which prevents them working properly as QBUS memories (i.e. in the PDP-11/83); they are only usable in the PDP-11/84. | ||
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| + | ==Markings== | ||
<pre> | <pre> | ||
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On the board | On the board | ||
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ASICs on board are 21-24404-01 and 21-22772-01 | ASICs on board are 21-24404-01 and 21-22772-01 | ||
</pre> | </pre> | ||
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| + | {{pdp-11}} | ||
Revision as of 19:25, 5 July 2018
The MSV11-J (M8637) is a QBUS/PMI DRAM main memory card. As a PMI card, it uses the CD interconnect; it can therefore only be plugged into a Q/CD backplane. NOTE: Plugging an MSV11-J card into a regular Q/Q backplane will damage the MSV11-J.
It has ECC which automagically corrects single-bit errors (at a slight penalty in response time), and detects double-bit errors. It holds up to 2 Mbyes when fully populated with 256Kx1 DRAM chips, or 1 Mbyte when half-populated (the only partially-filled configuration supported). It supports block mode on both the QBUS and PMI.
Although it can function in QBUS-only mode (but see the note below about the -JB and -JC versions), it is really intended for use with a PMI-capable CPU, such as the KDJ11-B. In systems such as the PDP-11/83, where the primary I/O bus is the QBUS, the card 'speaks' PMI to the CPU, and QBUS to the devices. In the PDP-11/84, the PMI is used for communication with both the CPU and the KTJ11-B UNIBUS adapter.
The memory is arranged as 2 banks, each 16 data bits wide, with 6 additional bits for the ECC. One bank is used to hold words at even locations, the other for those in odd; a read cycle from the bus will read both sides simultaneously, and so when in PMI mode, the second word is already available once the first has been sent.
On power-on, the system is frozen (via negation of the BPOK QBUS signal) while the memory is cleared, to prevent spurious ECC errors. For diagnostic purposes, the ECC can be disabled, and there are also means for the CPU to read/write the ECC bits directly.
Four versions exist:
- MSV11-JB, 1 Mbyte
- MSV11-JC, 2 Mbyte
- MSV11-JD, 1 Mbyte
- MSV11-JE, 2 Mbyte
The -JB and -JC are earlier versions which contain an error which prevents them working properly as QBUS memories (i.e. in the PDP-11/83); they are only usable in the PDP-11/84.
Markings
On the board M8637 Side 1 L1 50-15672-01 C1 Ga6618 2644711 2 MB Q,P-BUS MOS MEM LPWR TPB D.V0 On the metal frame P/N 1213113 M8651 EC ASICs on board are 21-24404-01 and 21-22772-01
