Difference between revisions of "DR11-C general device interface"
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The '''DR11-C general device interface''' was a [[UNIBUS]] [[device controller]] which provided a pair of 16-[[bit]] parallel ports, one input, and one output. It was a [[DEC card form factor|quad]] format card (M7860), and used an [[Small Peripheral Controller|SPC]] slot; it used [[programmed I/O]]. | The '''DR11-C general device interface''' was a [[UNIBUS]] [[device controller]] which provided a pair of 16-[[bit]] parallel ports, one input, and one output. It was a [[DEC card form factor|quad]] format card (M7860), and used an [[Small Peripheral Controller|SPC]] slot; it used [[programmed I/O]]. | ||
Revision as of 01:32, 26 February 2019
The DR11-C general device interface was a UNIBUS device controller which provided a pair of 16-bit parallel ports, one input, and one output. It was a quad format card (M7860), and used an SPC slot; it used programmed I/O.
Connection to the user's device is via a pair of 40-pin Berg connectors. A pair of optional single-width paddle cards (M971) may be connected via flat cables.
The DR11-C is the replacement for the earlier multi-board DR11-A General Device Interface. The DR11-C is slightly enhanced over the DR11-A (the -A does not have the CSR1/CSR0 bits).
Contents
Registers
The device has three control and buffer registers, which can be configured to any three sequential word locations in the I/O page; the first DR11-C is normally configured to addresses 767770-767774:
| Register | Abbreviation | Address |
|---|---|---|
| Control and Status Register | DRCSR | 767770 |
| Output Buffer Register | DROUTBUF | 767772 |
| Input Buffer Register | DRINBUF | 767774 |
In the register contents (below), bits which are read/write or unused are shown in normal font, those which are read-only are in italics.
Status Register (DRCSR)
| REQ B | Unused | REQ A | INT ENB A | INT ENB B | Unused | CSR1 | CSR0 | ||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
Output Buffer Register (DROUTBUF)
| OUT15 <-> OUT0 | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
Input Buffer Register (INBUF)
| IN15 <-> IN0 | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
