Difference between revisions of "UNICHANNEL 15 System"
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* An [[MX15-B Memory Multiplexer]], which allows the PDP-11 (both the CPU, and [[Direct Memory Access|DMA]] devices on the PDP-11's [[UNIBUS]]) access to the PDP-15's [[main memory]]. | * An [[MX15-B Memory Multiplexer]], which allows the PDP-11 (both the CPU, and [[Direct Memory Access|DMA]] devices on the PDP-11's [[UNIBUS]]) access to the PDP-15's [[main memory]]. | ||
| − | * A data channel between the two CPUs, which allows them to interrupt each other; this channel is implemented with a pair of [[DR11-C general device interface]] parallel ports, and a [[DR15 Device Interface]]. | + | * A data channel between the two CPUs, which allows them to interrupt each other; this channel is implemented with a pair of [[DR11-C general device interface]] parallel ports on the PDP-11, and a [[DR15 Device Interface]] on the PDP-15 end. |
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[[Category: DEC Processors]] | [[Category: DEC Processors]] | ||
Revision as of 15:46, 3 December 2019
The UNICHANNEL 15 System (UC15) is an group of hardware sub-systems which allows a PDP-15 to communicate with a PDP-11 (usually a PDP-11/05) which acts as an I/O front end, partially to offload the PDP-15's CPU, but also to allow PDP-15 systems access to devices which did not have native PDP-15 support, such as the RK05 disk drive. The UC15 includes two separate sub-systems:
- An MX15-B Memory Multiplexer, which allows the PDP-11 (both the CPU, and DMA devices on the PDP-11's UNIBUS) access to the PDP-15's main memory.
- A data channel between the two CPUs, which allows them to interrupt each other; this channel is implemented with a pair of DR11-C general device interface parallel ports on the PDP-11, and a DR15 Device Interface on the PDP-15 end.
