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Manufacturer: Digital Equipment Corporation
Year First Shipped: February, 1970
Form Factor: minicomputer
Word Size: 18 bits
Logic Type: TTL ICs
Clock Speed: 1.6 μsec (basic instructions)
Memory Speed: 0.8 μsec
Physical Address Size: 17 bits (128K words)
Virtual Address Size: 12 bits (direct), 15 bits (indirect), 17 bits (indexed)
Memory Management: bounds register; base and bounds pair (both optional)
Operating System: DECsys, Keyboard Monitor System, Foreground/Background System, DOS-15, XVM/DOS, XVM/RSX, XVM/MUMPS, Advanced Monitor System
Predecessor(s): PDP-9
Successor(s): None

The PDP-15 was DEC's last 18-bit computer, and the only one implemented using integrated circuits. Its principal intended use was for real-time systems. A variety of models were offered, from the PDP-15/10 (with 4K words of main memory), to the PDP-15/40 (with 24K words, and two disks).

Instructions had a 4-bit opcode, one bit of indirect, and one of indexing. It was a load-store architecture, with a single accumulator. There were several other specialized registers, including an 'Index Register', and a 'Limit Register' for loop control.

Both multiply/divide and floating point support were hardware options (the former being standard on all but the lowest model). The FP15 floating point unit was a complete separate processor, but shared the instruction set space with the basic CPU.

KM15 memory management included a boundary register to set the boundary between protected and un-protected memory, and two modes for the CPU. A memory relocation option, the KT15, with a base and bounds register pair, was also available.

A large range of peripherals were available, including DECtape (via the TC15 controller), fixed-head disk (RF15 controller), and RP02 large disk (RP15 controller).

Later models supported an interface (the UNICHANNEL-15, UC15) to a satellite PDP-11 (usually a PDP-11/05), through which other PDP-11-native peripherals could be supported, including DMA directly into the PDP-15's memory through the MX15-B Memory Multiplexer. These sometimes used the UNIBUS adapation for 18-bit mode, where the two parity lines were recycled into 2 extra data lines.

Further Reading

(All available online through BitSavers.)

  • "PDP-15 Systems Reference Manual"
  • "PDP-15 Systems User's Handbook: Volume I - Processor"
  • "PDP-15 Systems User's Handbook: Volume II - Peripherals"

External Links