Difference between revisions of "DPV11 synchronous serial line interface"

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[[Image:DPV11_M8020.jpg|250px|thumb|right|DPV11 M8020 board]]
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The '''DPV11''' is an early [[synchronous serial line]] [[peripheral|interface]] for the [[QBUS]] for a single line. Like the earlier [[UNIBUS]] synchronous serial line interfaces, it used [[programmed I/O]] (with separate receive and transmit [[interrupt]]s) to transfer data, and it was double-[[buffer]]ed for both input and output. It could operate in either [[half-duplex]] or [[full-duplex]], at [[baud rate]]s up to 56K bits/second (depending on [[software]] and system configuration).
 
The '''DPV11''' is an early [[synchronous serial line]] [[peripheral|interface]] for the [[QBUS]] for a single line. Like the earlier [[UNIBUS]] synchronous serial line interfaces, it used [[programmed I/O]] (with separate receive and transmit [[interrupt]]s) to transfer data, and it was double-[[buffer]]ed for both input and output. It could operate in either [[half-duplex]] or [[full-duplex]], at [[baud rate]]s up to 56K bits/second (depending on [[software]] and system configuration).
  

Revision as of 15:18, 20 October 2020

DPV11 M8020 board

The DPV11 is an early synchronous serial line interface for the QBUS for a single line. Like the earlier UNIBUS synchronous serial line interfaces, it used programmed I/O (with separate receive and transmit interrupts) to transfer data, and it was double-buffered for both input and output. It could operate in either half-duplex or full-duplex, at baud rates up to 56K bits/second (depending on software and system configuration).

The DVP11 used a Universal Synchronous Receiver/Transmitter (USRT) chip to implement the line protocol. Both byte-oriented (e.g. DDCMP, BISYNC) and bit-oriented (e.g. SDLC, HDLC) protocols were supported. (BISYNC support does not include some aspects, such as CRC generation and checking.) The character length was program-selectable to 5-8 bits (byte-oriented protocols) or 1-8 bits (bit-oriented). A variety of CRC algorithms were supported for error detection; the appropriate one could be selected depending on the protocol in use on the line.

The sync character was selectable under program control; the DPV11 could also be set to discard additional incoming sync characters in byte-oriented protocols. In character-oriented mode, it supported idling by sending the sync character; the line could also be set to a mark condition when not transmitting characters. In bit-oriented mode, either abort or flag characters

It was intended to interface to Bell 200 series modems (models 201, 208 and 209) and equivalents. It supported both RS-232 and RS-422 interface specifications; it had a complete set of modem control leads, and full modem control under program control. Local loopback for diagnostic] purposes could be set under program control; remote loopback as well, when a configuration jumper enabled setting it.

It was a dual card, the M8020; a Berg header on the card connected to a BC26L cable which led off to an EIA connector.

Registers

Register Abbreviation Address
Receive Control and Status Register RCSR 16xxx0
Receive Data and Status Register (read only) RDSR 16xxx2
Parameter Control Sync/Address Register (write only) PCSAR 16xxx2
Parameter Control and Character Length Register PCSCR 16xxx4
Transmit Data and Status Register TDSR 16xxx6


Read-only bits are shown in ITALICS; write-only bits are shown in BOLD; read/write bits are in normal font.

16xxx0: Receive Control and Status Register (RCSR)

F
DSC IC CTS RR RACT RCVST DMV SYNFLG RDRDY RIE DSIE REN LL RTS DTR SF/RL
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
  • DSC - Data Set Change
  • IC - Incoming Call
  • CTS - Clear to Send
  • RR - Receiver Ready; indicates the modem sees a carrier
  • RACT - Receive Active; set after the first character has been assembled
  • RCVST - Receiver Status Ready
  • DMV - Data Move
  • SYNFLG - Sync or Flag Detect
  • RDRDY - Receive Data Ready
  • RIE - Receive Interrupt Enable; allows an input interrupt when Receive Data Ready is set
  • DSIE - Data Set Interrupt Enable; allows an input interrupt when Data Set Change is set
  • REN - Receiver Enable
  • LL - Local Loopback
  • RTS - Ready to Send
  • DTR - Data Terminal Ready
  • SFRL - Select Frequency/Remote Loopback

16xxx2: Receive Data and Status Register (RDSR)

ERR ABC ROR RA EOM SOM RDAT
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
  • EC - Error Check
  • ABC - Assembled Bit Count
  • ROR - Receiver Overrun
  • RA - Received Abort
  • REOM - End of Message
  • RSOM - Start of Message
  • RDAT - Receive Data Buffer

16xxx2: Parameter Control Sync/Address Register (PCSAR)

APA PS SSLM SAMS IMS EDS SEC STA/RSYNC
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
  • APA - All Parties Addressed
  • PS - Protocol Select
  • SSLM - Strip Sync or Loop Mode
  • SAMS - Secondary Address Mode Select
  • IMS - Idle Mode Select
  • EDS - Error Detection Selection
  • SEC STA/RSYNC - Secondary Station Address / Sync Character

16xxx4: Parameter Control and Character Length Register (PCSCR)

TCL EAF ECF RCL Rsvd XIE SQ/TM XE MMS XBE XA DR
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
  • TCL - Transmitter Character Length
  • EAF - Extended Address Field
  • ECF - Extended Control Field
  • RCL - Receiver Character Length
  • XIE - Transmit Interrupt Enable
  • SQ/TM - Signal Quality / Test Mode
  • XE - Transmitter Enabled
  • MMS - Maintenance Mode Select
  • XBE - Transmitter Buffer Empty
  • XA - Transmitter Active
  • DR - Device Reset

16xxx6: Transmit Data and Status Register (TDSR)

XDL Reserved XGA ABORT EOF SOM TDBUF
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
  • XDL - Transmit Data Late
  • XGA - Transmit Go Ahead
  • ABORT - Transmit Abort
  • EOM - End of Message
  • SOM - Start of Message
  • TDBUF - Transmitter Data Buffer

See also

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