Difference between revisions of "DM11 Asynchronous 16-line Single-Speed Multiplexer"

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The '''DM11 asynchronous serial line interface''' was a very early [[UNIBUS]] [[peripheral]] which provided up to 16 [[asynchronous serial line]] connections. It was in some sense a predecessor to the [[DH11 asynchronous serial line interface|DH11]], in that it used [[Direct Memory Access|DMA]].
 
The '''DM11 asynchronous serial line interface''' was a very early [[UNIBUS]] [[peripheral]] which provided up to 16 [[asynchronous serial line]] connections. It was in some sense a predecessor to the [[DH11 asynchronous serial line interface|DH11]], in that it used [[Direct Memory Access|DMA]].
  
−
However, unlike any other UNIBUS peripheral, much of its internal state was actually stored in [[main memory]], not in [[register]]s in the device itself, using DMA to gain access to it. (Apparently this was early enough in time that [[gate]]s for registers were too expensive.) The data stored in memory included:
+
However, unlike any other UNIBUS peripheral, much of its internal state was actually stored in [[main memory]], not in [[register]]s in the device itself, using DMA to gain access to it. (Apparently this was early enough in time that [[gate]]s for [[flip-flop]]s for registers were too expensive, or took too much space on the [[printed circuit board|board]].) The data stored in memory included:
  
 
* per-line current output [[buffer]] [[address]]
 
* per-line current output [[buffer]] [[address]]
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(The 'input shift registers' are needed because no [[Asynchronous serial line#UART|UART]] [[integrated circuit|chips]] were used; the DM11 pre-dates their creation. The [[sampling]] of the incoming serial data stream, and the conversion to parallel form, was done in discrete [[logic]].)
 
(The 'input shift registers' are needed because no [[Asynchronous serial line#UART|UART]] [[integrated circuit|chips]] were used; the DM11 pre-dates their creation. The [[sampling]] of the incoming serial data stream, and the conversion to parallel form, was done in discrete [[logic]].)
  
−
The 64-[[character]] FIFO buffer made input over-runs unlikely. There were separate receive and transmit [[interrupt]]s, and [[half-duplex]] and [[full-duplex]] operation are supported in [[hardware]].
+
There were separate receive and transmit [[interrupt]]s, and [[half-duplex]] and [[full-duplex]] operation are supported in [[hardware]]. The 64-[[character]] FIFO buffer made input over-runs unlikely.  
  
 
The implementation of the basic '''DM11-AA''' used a custom double [[system unit]] [[backplane]], containing multiple cards; a [[flat cable]] connected this to separate rack-mounted [[DEC card form factor|dual-height]] [[DM11 distribution panel]] backplane (which required its own independent [[power supply]]).
 
The implementation of the basic '''DM11-AA''' used a custom double [[system unit]] [[backplane]], containing multiple cards; a [[flat cable]] connected this to separate rack-mounted [[DEC card form factor|dual-height]] [[DM11 distribution panel]] backplane (which required its own independent [[power supply]]).
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|Base Address Register          || DMBADR || 775006
 
|Base Address Register          || DMBADR || 775006
 
|}
 
|}
 +
 +
The Buffer Active Register has one bit per line to indicate that has output pending (described by the Current Address and Word Count tables below); the Break Status Register also has one bit per line. The Base Address Register is 8 bits wide, so the in-memory tables must start on a 0400 boundary.
  
 
The addresses shown are for the first DM11-AA11 in a system; additional ones (up to 16 total) are normally set to be at 775010, 775020, etc to 775170.
 
The addresses shown are for the first DM11-AA11 in a system; additional ones (up to 16 total) are normally set to be at 775010, 775020, etc to 775170.
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| TINT || TO || OVR || TIE || colspan=4 | Unused || DONE || RIE || colspan=2 | MEMEX  || Unused || MAINT || FHD || RENB
 
| TINT || TO || OVR || TIE || colspan=4 | Unused || DONE || RIE || colspan=2 | MEMEX  || Unused || MAINT || FHD || RENB
 
{{16bitoctal-bitout}}
 
{{16bitoctal-bitout}}
−
 
−
The Buffer Active Register has one bit per line to indicate that has output pending (described by the Current Address and Word Count tables below); the Break Status Register also has one bit per line. The Base Address Register is 8 bits wide, so the in-memory tables must start on a 0400 boundary.
 
  
 
==Memory tables==
 
==Memory tables==
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|}
 
|}
  
−
The first two are for transmitting, the last two for receiving. The format of the entries in the buffer is:
+
The first two are for transmitting, and defined the output buffer; the last two for receiving. The format of the entries in the input buffer is:
 
{{16bit-header}}
 
{{16bit-header}}
 
| Valid || Break || Parity || colspan="4" | Channel || Unused || colspan="8" style="text-align:center;" | Character
 
| Valid || Break || Parity || colspan="4" | Channel || Unused || colspan="8" style="text-align:center;" | Character

Revision as of 16:24, 26 December 2020

The DM11 asynchronous serial line interface was a very early UNIBUS peripheral which provided up to 16 asynchronous serial line connections. It was in some sense a predecessor to the DH11, in that it used DMA.

However, unlike any other UNIBUS peripheral, much of its internal state was actually stored in main memory, not in registers in the device itself, using DMA to gain access to it. (Apparently this was early enough in time that gates for flip-flops for registers were too expensive, or took too much space on the board.) The data stored in memory included:

  • per-line current output buffer address
  • per-line current output transfer length
  • per-line input shift registers
  • input buffer (a circular FIFO buffer)

(The 'input shift registers' are needed because no UART chips were used; the DM11 pre-dates their creation. The sampling of the incoming serial data stream, and the conversion to parallel form, was done in discrete logic.)

There were separate receive and transmit interrupts, and half-duplex and full-duplex operation are supported in hardware. The 64-character FIFO buffer made input over-runs unlikely.

The implementation of the basic DM11-AA used a custom double system unit backplane, containing multiple cards; a flat cable connected this to separate rack-mounted dual-height DM11 distribution panel backplane (which required its own independent power supply).

Modular 'line conditioning' units from the DF11 Communications Line Adapter series were installed in the distribution panel to allow support of either 20mA or EIA RS-232 serial lines. The alternative DC08CS distribution panel allowed connection to telegraph and Telex lines.

Lines could be connected to modems, provided the correct line conditioning units were installed, but modem control required a DM11-BB Modem Control Option, mounted in the main DM11 backplane along with the rest of the DM11 cards, and connected to the distribution panel via other flat cables which carried the modem control signals. The DM11-BB is logically a separate device from the DM11-AA, albeit one housed in the same DM11 backplane.

The line parameters:

  • baud rates (ranging from 45 to 1200)
  • character length (5-8 bits)
  • output stop bits (1 or 2)

were the same for all lines, and set by jumpers; parity was computed on incoming data. A 'break' condition on the line (i.e. continuous assertion) could also be generated and detected.

DM11-AA Device registers

Register Abbreviation Address
Status Register DMCSR 775000
Buffer Active Register DMBAR 775002
Break Status Register DMBSR 775004
Base Address Register DMBADR 775006

The Buffer Active Register has one bit per line to indicate that has output pending (described by the Current Address and Word Count tables below); the Break Status Register also has one bit per line. The Base Address Register is 8 bits wide, so the in-memory tables must start on a 0400 boundary.

The addresses shown are for the first DM11-AA11 in a system; additional ones (up to 16 total) are normally set to be at 775010, 775020, etc to 775170.

775000: Status Register (DMCSR)

TINT TO OVR TIE Unused DONE RIE MEMEX Unused MAINT FHD RENB
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Memory tables

The four tables of per-line data kept in main memory were:

Table Offset (in bytes) Size (in bytes)
Current Address 0 32
Word Count 040 32
Bit Assembly 0100 32
Circular Buffer 0200 128

The first two are for transmitting, and defined the output buffer; the last two for receiving. The format of the entries in the input buffer is:

Valid Break Parity Channel Unused Character
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

The input character, which may be less than 8 bits wide, is stored right-justified.

Implementation

The DM11-AA boards (all quad, except for the Control C, which is a dual) which plugged into the DM11 backplane are:

  • M7240 - Control A
  • M7241 - Control B
  • M7242 - Control C
  • M7243 - Transmitter D
  • M7244 - Transmitter E
  • M7244 - Receiver

and 4 single-width, non-DM11-specific cards:

  • M782 - Interrupt control (two)
  • M105 - Address selection
  • M405 - Clock

Board locations (as seen from the board insertion side of the backplane, not the wire-wrap pin side, as is common in DEC documentation) are:

Connector
Slot A B C D E F
1 UNIBUS In M7240
2 M105 M7241
3 Power M405 M782 M782 M7242
4 M974 Cable M7245
1   M7244
2   M7243
3 Power Reserved for DM11-BB
4 UNIBUS Out Reserved for DM11-BB

(NOTE: The document which is the source for this table has two different cards marked as 'M7245', and no 'M7243's. So it clearly has errors, but it's not obvious what they all are.)

Power comes in on a single-width stub card in the A3 slots (as is canonical in the PDP-11/20 generation of PDP-11s).

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