Difference between revisions of "PDP-9"

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Its principal intended use was for [[real-time system]]s, including data recording and process control. A variety of models were offered; the basic system provided 8K words of [[core memory]], and the PDP-9/L was a cost-reduced system with cheaper peripherals and 4KW of memory.
 
Its principal intended use was for [[real-time system]]s, including data recording and process control. A variety of models were offered; the basic system provided 8K words of [[core memory]], and the PDP-9/L was a cost-reduced system with cheaper peripherals and 4KW of memory.
  
[[Instruction]]s had a 4-bit opcode, 1 bit of indirect, and 13 bits of address. It was a [[load-store architecture]], with a single [[accumulator]]. It used hard-wired [[core memory]], similar to that in the [[Apollo Guidance Computer]], for the high-speed [[read-only memory|ROM]] needed for a microcoded design. Each [[microinstruction]] contained the [[address]] of the next one; there was no micro-[[Program Counter|PC]].
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[[Instruction]]s had a 4-bit opcode, 1 bit of indirect, and 13 bits of address. It was a [[load-store architecture]], with a single [[accumulator]]. For the high-speed [[read-only memory|ROM]] needed for a microcoded design, it used hard-wired [[core memory]], similar to that in the [[Apollo Guidance Computer]]. [[Microinstruction]]s were 36 bits wide, of which 6 were the 'control memory address', the [[address]] of the next one; there was no micro-[[Program Counter|PC]]. Conditional micro-branching was available by modifying the CMA during that microinstruction.
  
Multiply/divide was a hardware option, the KE09A [[Extended Arithmetic Element]], which also performed shifting. Use of more than 8KW of [[main memory]] required the Memory Extension Control, KG09A. A [[memory management]] option, the KX09A, which included a boundary [[register]] to set the boundary between protected and un-protected memory, and two modes for the CPU, was also available.
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Multiply/divide was a hardware option, the KE09A [[Extended Arithmetic Element]], which also performed shifting. Use of more than 8KW of [[main memory]] (all core in the PDP-9) required the Memory Extension Control, KG09A. A [[memory management]] option, the KX09A, which included a boundary [[register]] to set the boundary between protected and un-protected memory, and two modes for the CPU, was also available.
  
 
The KF09A Automatic Priority Interrupt option provided 8 levels of [[interrupt]] priority, each of which could support up to 8 [[peripheral|devices]]. Each device could provide its own [[interrupt vector]]. The DM09 [[Direct Memory Access]] Channel Multiplexor Adapter provided high-speed devices with direct access to main memory for data transfers.
 
The KF09A Automatic Priority Interrupt option provided 8 levels of [[interrupt]] priority, each of which could support up to 8 [[peripheral|devices]]. Each device could provide its own [[interrupt vector]]. The DM09 [[Direct Memory Access]] Channel Multiplexor Adapter provided high-speed devices with direct access to main memory for data transfers.

Revision as of 13:10, 5 May 2021


PDP-9
Manufacturer: Digital Equipment Corporation
Year First Shipped: 1966
Form Factor: minicomputer
Word Size: 18 bits
Logic Type: PNP Transistor FLIP CHIPs
Design Type: microcoded
Memory Speed: 1 μsec
Physical Address Size: 15 bits (32K words)
Virtual Address Size: 13 bits (direct), 15 bits (extended)
Memory Management: bounds register
Predecessor(s): PDP-7
Successor(s): PDP-15
Price: US$30K (8KW system)


The PDP-9 was DEC's fourth 18-bit computer, and the first DEC CPU to use microcode. A little over 400 were built.

Its principal intended use was for real-time systems, including data recording and process control. A variety of models were offered; the basic system provided 8K words of core memory, and the PDP-9/L was a cost-reduced system with cheaper peripherals and 4KW of memory.

Instructions had a 4-bit opcode, 1 bit of indirect, and 13 bits of address. It was a load-store architecture, with a single accumulator. For the high-speed ROM needed for a microcoded design, it used hard-wired core memory, similar to that in the Apollo Guidance Computer. Microinstructions were 36 bits wide, of which 6 were the 'control memory address', the address of the next one; there was no micro-PC. Conditional micro-branching was available by modifying the CMA during that microinstruction.

Multiply/divide was a hardware option, the KE09A Extended Arithmetic Element, which also performed shifting. Use of more than 8KW of main memory (all core in the PDP-9) required the Memory Extension Control, KG09A. A memory management option, the KX09A, which included a boundary register to set the boundary between protected and un-protected memory, and two modes for the CPU, was also available.

The KF09A Automatic Priority Interrupt option provided 8 levels of interrupt priority, each of which could support up to 8 devices. Each device could provide its own interrupt vector. The DM09 Direct Memory Access Channel Multiplexor Adapter provided high-speed devices with direct access to main memory for data transfers.

A large range of peripherals were available, including DECtape (via the TC02 controller), magnetic tape (via the TC59), drum (RM09 controller) and fixed-head disk (RB09; and RS09, via the RF09 controller). The RM09 and RB09 use the DM09.

Further reading

(All available online through BitSavers.)

External links