Difference between revisions of "CD11 High-Speed Punched Card Reader Control Unit"
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Revision as of 00:45, 3 November 2022
The CD11 High-Speed Punched Card Reader Control Unit was a UNIBUS device controller for the CR04 punched card reader. It used DMA to transfer data.
Contents
Registers
The controller has four control and buffer registers, which can be configured to any four sequential word locations in the I/O page; it is normally configured to addresses 772460-774666:
Register | Abbreviation | Address |
---|---|---|
Status and Control Register | CDST | 772460 |
Column Count Register | CDCC | 772462 |
Current Address Register | CDBA | 772464 |
Data Buffer Register | CDDB | 772466 |
In the register contents (below), bits which are read/write or unused are shown in normal font, those which are read-only are in italics, and write-only in bold.
Status and Control Register (CDST)
ERR | HDR CHK | EOF | OFFLINE | DATA ERR | DATA LT | NXM | PWR CLR | RDY | INT ENB | EXT BUS ADDR | RDR ONLINE | HOPPER CHECK | DATA PACK | READ | |
15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
Column Count Register (CDCC)
CC15 <---> CC00 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
Current Address Register (CDBA)
BA15 <---> BA00 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
Data Buffer Register (CDDB)
The format of the contents this register depends on the setting of the 'Data Packing' bit in the CSR. If 0, '12-bit word', it holds 12-bit raw data from the card:
Unused | Zones 12-11 | Zones 0-9 | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
If 1, '8-bit byte', it holds the compressed Hollerith code (zones 1-7 can have only a single punch, which is encoded in octal in 3 bits; a '0' means 'no punch in any of these'):
Unused | Zone 12 | Zone 11 | Zone 0 | Zone 9 | Zone 8 | Code Zones 1-7 | |||||||||
15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
Implementation
It was constructed from a number of smaller FLIP CHIPs which were installed in custom 4-slot system unit backplane. The modules are:
- M112 - 10 x 2-input NOR gates
- 2 x M113 - 10 x 2-input NAND gates
- M117 - 6 x 4-input NAND gates
- M203 - 8 x 'S-R' flip-flops
- M205 - 5 x 'D' flip-flops
- M239 - 3 x 4-bit counter/register
- M304 - One-shot delay
- M611 - High speed power inverters
- M721 - Bus interface
- M7249 - Hollerith check
- M783 - Bus drivers
- M784 - Bus receivers
- M796 - UNIBUS Master Control
- M7821 - Interrupt Control
- M957 - Ribbon cable connector
- M7219 - Bus Interface
The M7219 is a quad card; the others are all single. (Of those, the M783, M784, M796, M7821 and M957 are extended length; most of the others are all standard length.)
Board locations (as seen from the board insertion side of the backplane, not the wire-wrap pin side, as is common in DEC documentation) are:
Connector | ||||||
---|---|---|---|---|---|---|
Slot | A | B | C | D | E | F |
1 | UNIBUS In | M7219 | ||||
2 | M721 | M957 | M784 | M783 | M7821 | M796 |
3 | M113 | M239 | M7249 | M611 | M117 | M205 |
4 | UNIBUS Out | M113 | M112 | M304 | M203 |
External links
- pdp11 peripherals handbook (1976) - the CD11 is covered on pp. 60-72 of the PDF
- KS10-Based DECSYSTEM-2020 Technical Manual (EK-0KS10-TM-002) - the CD11 is covered on pp. 22-25 of the PDF