Difference between revisions of "BBN Pager"
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Revision as of 05:16, 6 January 2024
The BBN Pager was an add-on device for the KA10 Central Processing Unit to provide virtual memory capability, designed and built by BBN (much as the MIT AI Lab added hardware to their KA10 for the same purpose). DEC had provided only basic memory management capabilities on the KA10 - a pair of base and bounds registers, one for each half of the address space.
It supported splitting the address space into 512 pages, each 512 words long; 'user' and 'executive' modes on the KA10 had separate page tables.
It was used to support the TENEX operating system - although one was also added to the KA10 at SAIL, which ran WAITS. Quite a few were built for other organizations which had KA10's, to allow them to run TENEX.
Technical Details
The Pager was a separate unit inserted into the PDP-10 Memory Bus between the CPU and the system's memories. It also required minor changes to the KA10; both to provide signals required for the operation of the Pager (which were carried to the Pager by two separate cables), and also to make changes to the CPU required by the operating system (such as extra, specialized, instructions).
The pager contained a cache of page table translation entries held in 'associative registers'; the basic complement was 16 associative registers, but it would operate with as few as 1, or it could be expanded to up to 54 associative registers.
