Memory Test Computer

The Memory Test Computer was an early vacuum tube computer which was a spin-off of the pioneering Whirlwind effort; it was built by Ken Olsen and others to test the first core memory, devised for Whirlwind. It was a parallel computer, with a 16-bit word length (since the memory it was to test was for Whirlwind, which was that size); it was similar in many other ways to Whirlwind, also.

It first ran in March, 1953; the prototype core memory was installed and operational by the end of May. Later, the MTC was used to test various system components to be used in the SAGE system. It was shut down permanently on March 21, 1958; but unlike Whirlwind and the later TX-0, it unfortunately was apparently not preserved. It was a considerable influence on the TX-0, through people who had worked on the MTC.

Technical details

The MTC had had 26 instructions; for main memory it had 4KW of core memory (after the main core memory unit had been moved to Whirlwind), a drum (originally only 4KW in size), and 64W of ROM, implemented in a toggle switch array and a plug-board. (NB: memory locations are referred to as "registers" in the documentation.) Addresses consisted of a 4-bit 'field number' and an 11-bit 'address' within that field; field 0 was the ROM, 1 and 2 were the core, and 3 and 4 were the drum. The pair of a field number and an address were termed an 'extended address'.

Most registers and data paths had an additional bit, for parity error checking. Bits were numbered using big-endian notation; the MTC used one's complement arithmetic (overflows cause an 'overflow alarm', which halts the MTC). For I/O it had two paper tape readers and a punch, printers, and several displays (one with a camera controlled by the MTC).

Registers

There were 11 visible registers (built out of flip-flops) in the final design:

Function	Name	Size (bits)	Use	Comment
PC		11	Program Counter
Partial Sum		16?	General purpose	Together termed the 'Accumulator (AC)', but that name was often informally applied to the Partial Sum Register
Carry		1?	Momentarily store carries generated in addition operations
A	AR	16	Buffer register between all the data sources and sinks in the system; connected to 'A-Register-In' and 'A-Register-Out' buses
B	BR	16	Effectively an extension of the PSR during multiplications
Live Register 1	LR1	16	Can be substituted for any ROM location	Addressed as main memory in field 0
Live Register 2	LR2	16	Can be substituted for any plug-board location
Live Register 5	LR5	16
Live Register 3	LR3?	16
Live Register 4	LR4?	16
Operation Field Register		4?	Can only be written, not read
Program Field Register		4?		Loading does not take immediate effect

Instructions

Instruction words contained a 5-bit operation code, and 11 bits of address - although in some instructions the 'address' field is used for other purposes. Since the address portion was not long enough to hold an extended address, the MTC used bank switching to gain access to all of main memory.

Opcode	Abbreviation	Function	Comment
0	ha	Halt machine
1	mh	Multiply AC by memory, leave result in BR,AC
2	ds	Display memory contents
3	ic	'Identity check'; compares AC with memory contents
4	st	Store AC in memory
6	ra	'Replace address'; stores bits 5-15 of AC in memory
7	rf	'Return from'; stores bits 5-15 of LR2 in memory
8	ca	'Clear and add'; load AC from memory
9	ad	Add memory to AC
10	cs	'Clear and subtract'; load AC with negative of memory
11	su	Subtract memory from AC
12	et	'Extract'; AND memory into AC
14	ch	'Charactron display'	Refer to Programming Manual
15	sm	'Subtract Magnitudes'; copy AC to BR, subtract memory from AC
16	tr	'Transfer'; load memory address into PC	Consult Programming Manual for side-effects on LR2
17	tro	'Transfer Out'; load memory address into PC, update field of PC from Program Field Register
18	tn	'Transfer on negative'; if AC is negative, as 'tr' above
19	tno	'Transfer on negative out'; if AC is negative, as 'tro' above
20	md	'Memory address display'	Refer to Programming Manual
21	sof	'Select operation field'; load Operation Field Register
22	to	'Transfer on overflow'; if an overflow condition exists, as 'tr' above
24	cr	'Cycle right'	Refer to Programming Manual
25	sr	'Shift right'
28	pr	'Print/punch'
30	ri	'Read in'
31	op	'Operate'

External links

• MTC - documents at Bitsavers
  • Memory Test Computer: Programming Manual
• Memory Test Computer Memoranda, 1952-1958
• C. Gordon Bell, Gerald Butler, Robert Gray, John E. Mcnamara, Donald Vonada, and Ronald Wilson, The PDP-1 and Other 18-Bit Computers, in C. Gordon Bell, J. Craig Mudge, John. E. McNamara, Computer Engineering: A DEC View of Hardware Systems Design, Digital Press, Bedford, 1978 - contains some detail about the MTC
• Dick Best and Wally Wheaton with Memory Test Computer at MIT