Difference between revisions of "Small Peripheral Controller"
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SPC slots were wired to bring all 5 UNIBUS [[bus grant line|grant lines]] through the device; this was performed in rows C (for [[Non-Processor Request and Grant|NPG]]) and D (for BGx). | SPC slots were wired to bring all 5 UNIBUS [[bus grant line|grant lines]] through the device; this was performed in rows C (for [[Non-Processor Request and Grant|NPG]]) and D (for BGx). | ||
| − | The device board generally had a header which routed the grant (and matching request) line for the desired priority level to the [[interrupt]] [[circuit]]ry, and passed the other grant lines through. Un-occupied slots needed to have a [[G727 grant continuity card|G727]] installed. | + | The device board generally had a [[UNIBUS priority plug]] header which routed the grant (and matching request) line for the desired priority level to the [[interrupt]] [[circuit]]ry, and passed the other grant lines through. Un-occupied slots needed to have a [[G727 grant continuity card|G727]] installed. |
The NPG grant line generally had a [[jumper]] on the backplane at each slot (between pins CA1 and CB1), which had to be removed if a [[DMA]] device was plugged into that slot, or installed if one was removed; alternatively, a [[G7273 grant continuity card]] could be installed. | The NPG grant line generally had a [[jumper]] on the backplane at each slot (between pins CA1 and CB1), which had to be removed if a [[DMA]] device was plugged into that slot, or installed if one was removed; alternatively, a [[G7273 grant continuity card]] could be installed. | ||
Latest revision as of 18:01, 27 July 2025
Small Peripheral Controller or SPC was DEC's name for a board slot in the backplanes of UNIBUS PDP-11s into which small device controllers, etc, could be plugged. It was a quad-high slot, occupying rows C-F in a hex slot.
It was originally conceived to hold a dual-height device-specific card, along with single-height M105 Address Selector and M782 Interrupt Control FLIP CHIPs (later, the M7820 and M7821 revisions). (Among the dual-width controllers which did this were the KL11 (M780), the PC11 (M781), the DR11-A (M786), and the CR11 (M829).)
The appropriate UNIBUS signal lines (address, data, etc) were thus wired to the appropriate rows/pins in SPC slots. Other pins were wired to allow the necessary communication between the cards, without requiring cables between them.
It soon became more cost-effective to fabricate an entire device on a single quad card, but the pinout was retained. (For the pinout of an SPC slot, see here.)
Contents
Grants
SPC slots were wired to bring all 5 UNIBUS grant lines through the device; this was performed in rows C (for NPG) and D (for BGx).
The device board generally had a UNIBUS priority plug header which routed the grant (and matching request) line for the desired priority level to the interrupt circuitry, and passed the other grant lines through. Un-occupied slots needed to have a G727 installed.
The NPG grant line generally had a jumper on the backplane at each slot (between pins CA1 and CB1), which had to be removed if a DMA device was plugged into that slot, or installed if one was removed; alternatively, a G7273 grant continuity card could be installed.
SPC Extensions
On some systems, some SPC pins were recycled for other purposes.
In the PDP-11/04 and PDP-11/34, on the DD11-P backplane which holds the CPU card(s), along with the KY11-LB Programmer's Console (which plugs into an otherwise-standard SPC slot), the CPU and the Programmer's Console do some communication via the backplane. Pins CP1 and CR1 are Halt Request and Halt Grant, respectively; they allow the KY11-B to tell the CPU to halt.
Pinout
The following table gives the pinout of an SPC slot. Pins are identified in the standard DEC manner. There are four connectors in a slot, C, D, E and F; pins on the component side are 1, those on the solder side are 2. Pins are identified by the 'DEC alphabet', A-V, with G, I, O and Q dropped.
| Signal | Assertion | Termination | Pin |
|---|---|---|---|
| Initialization and Shutdown | |||
| DC LO | L | Slow | CN1 |
| AC LO | L | Slow | CV1 |
| INIT | L | Fast | DL1 |
| Arbitration | |||
| NPR | L | Fast | FJ1 |
| BR7 | L | Fast | DD2 |
| BR6 | L | Fast | DE2 |
| BR5 | L | Fast | DF2 |
| BR4 | L | Fast | DH2 |
| NPG | H | Grant | In-CA1; Out-CB1 |
| BG7 | H | Grant | In-DK2; Out-DL2 |
| BG6 | H | Grant | In-DM2; Out-DN2 |
| BG5 | H | Grant | In-DP2; Out-DR2 |
| BG4 | H | Grant | In-DS2; Out-DT2 |
| SACK | L | Fast | FT2 |
| Addressing | |||
| A00 | L | Fast | EH2 |
| A01 | L | Fast | EH1 |
| A02 | L | Fast | EF1 |
| A03 | L | Fast | EV2 |
| A04 | L | Fast | EU2 |
| A05 | L | Fast | EV1 |
| A06 | L | Fast | EU1 |
| A07 | L | Fast | EP2 |
| A08 | L | Fast | EN2 |
| A09 | L | Fast | ER1 |
| A10 | L | Fast | EP1 |
| A11 | L | Fast | EL1 |
| A12 | L | Fast | EC1 |
| A13 | L | Fast | EK2 |
| A14 | L | Fast | EK1 |
| A15 | L | Fast | ED2 |
| A16 | L | Fast | EE2 |
| A17 | L | Fast | ED1 |
| Data | |||
| D00 | L | Fast | CS2 |
| D01 | L | Fast | CR2 |
| D02 | L | Fast | CU2, FE2% |
| D03 | L | Fast | CT2, FL1% |
| D04 | L | Fast | CN2, FN2% |
| D05 | L | Fast | CP2, FF1% |
| D06 | L | Fast | CV2, FF2% |
| D07 | L | Fast | CM2, FH1% |
| D08 | L | Fast | CL2, FK1% |
| D09 | L | Fast | CK2 |
| D10 | L | Fast | CJ2 |
| D11 | L | Fast | CH1 |
| D12 | L | Fast | CH2 |
| D13 | L | Fast | CF2 |
| D14 | L | Fast | CE2 |
| D15 | L | Fast | CD2 |
| Control | |||
| C0 | L | Fast | EJ2 |
| C1 | L | Fast | EF2 |
| PA | L | Fast | CC1 |
| PB | L | Fast | CS1 |
| BBSY | L | Fast | FD1 |
| MSYN | L | Fast | EE1 |
| INTR | L | Fast | FM1 |
| SSYN | L | Fast | EJ1, FC1% |
| Power | |||
| Ground | N/A | N/A | xC2 |
| Ground | N/A | N/A | xT1 |
| +5 | N/A | N/A | xA2 |
| -15 | N/A | N/A | xB2 |
Entries of the form 'xYN' mean that that is available on all 4 connectors (C, D, E and F) in each slot.
% For forward compatibility, use the first pin rather than the second.
