UNIBUS
The UNIBUS was the earliest of two bus technologies used with PDP-11s manufactured by Digital Equipment Corporation; it was first seen in the PDP-11/20, in 1972. Later, early VAX systems from that company used the Unibus as an I/O bus.
It was the only bus in most PDP-11 systems, and thus supported several capabilities: the ability of the processor to read and write main memory, and device registers; and the ability for devices to do DMA transfers to memory, and interrupt the CPU.
The UNIBUS contained 16 data lines, and 18 address lines; the 18 address lines allowed the addressing of a maximum of 256 KBytes. Typically, the top 8 KBytes was reserved for the registers of the memory mapped IO devices used in the PDP-11 architecture. (The limit of 18 address lines was to prove a severe handicap in the later phases of the UNIBUS' operational life.)
The bus was completely asynchronous, allowing a mixture of fast and slow devices. It allowed the overlapping of arbitration (selection of the next bus master) while the current bus master was still performing data transfers.
The design deliberately minimized the amount of redundant logic required in the system. For example, a system always contained more slave devices than master devices so most of the fancy logic required to implement asynchronous data transfers was forced into the relatively few master devices. For interrupts, only the interrupt-fielding processor needed to contain the complicated timing logic.
The end result was that most I/O controllers could be implemented with very simple logic; most of the critical logic was later implemented as a custom MSI IC.
The UNIBUS was composed of 72 wires (2 connectors x 36 lines per connector). When not counting the power and ground lines, it is usually referred to as a 56 line bus. It could exist on a cable (the original mode of operation), and later, within a backplane (in 'Small Peripheral Controller (SPC)' or 'Modified Unibus (MUD)' slots).
Up to 20 nodes (devices) could be connected to a single UNIBUS segment; additional segments could be connected via a bus repeater.
Technical details
18 A00-A17 - Address Lines 16 D00-D15 - Data Lines 4 BR4-BR7 - Bus (Interrupt) Requests at priorities 4 (lowest) through 7 (highest) 4 BG4-BG7 - Bus (Interrupt) Grants at priorities 4 (lowest) through 7 (highest) 1 NPR - Non Processor (DMA) Request 1 NPG - Non Processor (DMA) Grant 1 ACLO - AC Low 1 DCLO - DC Low 1 MSYNC - Master Sync 1 SSYNC - Slave Sync 1 BBSY - Bus Busy 1 SACK - Selection Acknowledge 1 INIT - Bus Init 1 INTR - Interrupt Request 1 PA - Parity control 1 PB - Parity control 2 C0-C1 - Cyce Control Lines: 2 +5v - Power Lines (not counted as part of the 56) 14 Gnd - Ground Lines (not counted as part of the 56)
The two control lines (C0 and C1) allowed the selection of four different data transfer cycles:
- DATI (Data In, a read)
- DATIP (Data In/Pause, the first portion of a Read-Modify-Write operation. A DATO or DATOB operation completes this.)
- DATO (Data Out, a word write)
- DATOB (Data Out/Byte, a byte write)
During an interrupt cycle, a fifth style of transfer was automatically invoked to convey an interrupt vector from the interrupting device to the interrupt-fielding processor.
